Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "arm64: dts: qcom: sm8150: Add cpufreq HW device node"

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qctecmdr
2022-04-26 10:06:20 -07:00
committed by Gerrit - the friendly Code Review server
parent 85fbaf082c 7116bce820
commit bd5d7907ae
1 changed files with 22 additions and 0 deletions
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22
qcom/sm8150.dtsi
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@@ -51,6 +51,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -77,6 +78,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -97,6 +99,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_2>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -117,6 +120,7 @@
i-cache-size = <0x8000>;
d-cache-size = <0x8000>;
next-level-cache = <&L2_3>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
@@ -137,6 +141,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_4>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -157,6 +162,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_5>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -177,6 +183,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_6>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
@@ -197,6 +204,7 @@
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
next-level-cache = <&L2_7>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
@@ -873,6 +881,20 @@
#clock-cells = <1>;
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0x18323000 0x1400>, <0x18325800 0x1400>,
<0x18327800 0x1400>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
qcom,no-accumulative-counter;
#freq-domain-cells = <2>;
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,