Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add bindings for RSC and PDC devices for sdxpinn"

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qctecmdr
2022-07-07 06:11:44 -07:00
committed by Gerrit - the friendly Code Review server
parent 3e780712a2 b9f09c5ef2
commit bf1119b744
2 changed files with 37 additions and 0 deletions
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1
bindings/interrupt-controller/qcom,pdc.txt
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@@ -24,6 +24,7 @@ Properties:
- "qcom,sdm8150-pdc": For SM8150
- "qcom,sdm8250-pdc": For SM8250
- "qcom,sdm8350-pdc": For SM8350
- "qcom,sdxpinn-pdc": For SDXPINN
- reg:
Usage: required

36
qcom/sdxpinn.dtsi
View File

@@ -2,6 +2,7 @@
#include <dt-bindings/clock/qcom,gcc-sdxpinn.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
model = "Qualcomm Technologies, Inc. SDXPINN";
@@ -145,6 +146,31 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
apps_rsc: rsc@17a00000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x17a00000 0x10000>,
<0x17a10000 0x10000>,
<0x17a20000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
qcom,drv-count = <3>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
apps_rsc_drv2: drv@2 {
qcom,drv-id = <2>;
qcom,tcs-offset = <0xd00>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 3>,
<SLEEP_TCS 2>,
<WAKE_TCS 2>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 1>;
};
};
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
@@ -213,6 +239,15 @@
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sdxpinn-pdc", "qcom,pdc";
reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
qcom,pdc-ranges = <0 147 52>, <52 558 91>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
@@ -363,6 +398,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
};
ipcc_mproc: qcom,ipcc@408000 {