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ARM: dts: msm: gunyah: Add qtmr binding

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Add qtmr binding description and requirments which include
compatible, reg, interrupts and interrupts name.

Change-Id: I6bc11b30cb05876475bd43148b072e93dfaf5006
This commit is contained in:
Po-Jung Lai
2021-10-04 17:10:26 -07:00
parent 879af02fc6
commit c3e1184a5f
1 changed files with 27 additions and 0 deletions
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bindings/soc/qcom/qcom,gh-qtmr.txt Normal file
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QCT Gunyah Hypervisor irq Lending Test Driver
The Gunyah Hypervisor Test Driver is used to validate gunyah hypervisor
functionality. It includes test node for gunyah irq lending between vms.
Qtime timer and irq will be lended between vms.
Required properties:
- compatible: "qcom,gh-qtmr"
- reg: Pairs of physical base addresses and region sizes of
memory mapped registers.
- reg-names: Names of the bases for the above registers. Expected
bases are: "qtmr-base"
- interrupts: Lists the threshold IRQ.
- interrupt-names: Names of the interrupts.
- qcom,primary or qcom,secondary: primary is for PVM / secondary is for SVM
Example:
qcom,gh-qtimer@17425000{
compatible = "qcom,gh-qtmr";
reg = <0x17425000 0x1000>;
reg-names = "qtmr-base";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qcom,qtmr-intr";
qcom,primary;
};