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dt-bindings: interconnect: add EPSS L3 bindings for Cinder

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Add interconnect device bindings for EPSS L3 for Cinder.

Change-Id: I0a1d5660d3c4a8d491790005b5762d899f8144cf
This commit is contained in:
Odelu Kukatla
2022-05-31 10:05:02 +05:30
parent f490eaa904
commit e87179568d
1 changed files with 1 additions and 10 deletions
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11
bindings/interconnect/qcom,epss-l3.txt
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@@ -6,7 +6,7 @@ performance states of the CPU subsystem.
Required properties :
- compatible : shall contain only one of the following:
"qcom,lahaina-epss-l3-shared",
"qcom,cinder-epss-l3-cpu",
"qcom,lahaina-epss-l3-cpu";
- reg : Address and length of the register set for the device
- clock-names: should contain "xo", "alternate"
@@ -16,15 +16,6 @@ Required properties :
Examples:
epss_l3_shared: l3_shared@18590000 {
reg = <0x18590000 0x1000>;
compatible = "qcom,lahaina-epss-l3-shared";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_GPLL0>;
};
epss_l3_cpu: l3_cpu@18590000{
reg = <0x18590000 0x4000>;
compatible = "qcom,lahaina-epss-l3-cpu";