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dt-bindings: interconnect: add EPSS L3 bindings

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Add bindings for the new interconnect EPSS L3 driver.

Change-Id: I812f0fd9690b3c5489e8d4d37e685dab03e84a97
This commit is contained in:
Odelu Kukatla
2022-05-31 09:59:26 +05:30
parent 82b82b5b1a
commit f490eaa904
1 changed files with 35 additions and 0 deletions
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bindings/interconnect/qcom,epss-l3.txt Normal file
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Qualcomm Technologies, Inc. EPSS L3 interconnect driver binding
-----------------------------------------------------------
The EPSS L3 Interconnect provider supports the scaling of L3 cache
performance states of the CPU subsystem.
Required properties :
- compatible : shall contain only one of the following:
"qcom,lahaina-epss-l3-shared",
"qcom,lahaina-epss-l3-cpu";
- reg : Address and length of the register set for the device
- clock-names: should contain "xo", "alternate"
- clocks: list of phandle and clock specifier pairs corresponding to
entries in the clock-names property.
- #interconnect-cells : should contain 1
Examples:
epss_l3_shared: l3_shared@18590000 {
reg = <0x18590000 0x1000>;
compatible = "qcom,lahaina-epss-l3-shared";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_GPLL0>;
};
epss_l3_cpu: l3_cpu@18590000{
reg = <0x18590000 0x4000>;
compatible = "qcom,lahaina-epss-l3-cpu";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_GPLL0>;
};