ARM: dts: msm: Add initial devicetrees for sdxbaagha target

Add initial devicetree files for supporting sdxbaagha target.

Change-Id: I0a73ebe1776cfb9d2c3a27ac55aa2c82244c83f2

bindings/arm/msm/msm.txt

@@ -110,6 +110,9 @@ SoCs:
 - MONACO
   compatible = "qcom,monaco", "qcom,monacop"
 
+- SDXBAAGHA
+  compatible = "qcom,sdxbaagha"
+
 Generic board variants:
 
 - CDP device:
@@ -309,3 +312,6 @@ compatible = "qcom,sdxpinn-mtp"
 compatible = "qcom,sdxpinn-cdp"
 compatible = "qcom,sa410m-rumi"
 compatible = "qcom,quinvm"
+compatible = "qcom,sdxbaagha-rumi"
+compatible = "qcom,sdxbaagha-mtp"
+compatible = "qcom,sdxbaagha-cdp"

bindings/interrupt-controller/arm,gic.txt

@@ -0,0 +1,171 @@
+* ARM Generic Interrupt Controller
+
+ARM SMP cores are often associated with a GIC, providing per processor
+interrupts (PPI), shared processor interrupts (SPI) and software
+generated interrupts (SGI).
+
+Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
+Secondary GICs are cascaded into the upward interrupt controller and do not
+have PPIs or SGIs.
+
+Main node required properties:
+
+- compatible : should be one of:
+	"arm,arm1176jzf-devchip-gic"
+	"arm,arm11mp-gic"
+	"arm,cortex-a15-gic"
+	"arm,cortex-a7-gic"
+	"arm,cortex-a9-gic"
+	"arm,eb11mp-gic"
+	"arm,gic-400"
+	"arm,pl390"
+	"arm,tc11mp-gic"
+	"brcm,brahma-b15-gic"
+	"nvidia,tegra210-agic"
+	"qcom,msm-8660-qgic"
+	"qcom,msm-qgic2"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source.  The type shall be a <u32> and the value shall be 3.
+
+  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
+  interrupts.
+
+  The 2nd cell contains the interrupt number for the interrupt type.
+  SPI interrupts are in the range [0-987].  PPI interrupts are in the
+  range [0-15].
+
+  The 3rd cell is the flags, encoded as follows:
+	bits[3:0] trigger type and level flags.
+		1 = low-to-high edge triggered
+		2 = high-to-low edge triggered (invalid for SPIs)
+		4 = active high level-sensitive
+		8 = active low level-sensitive (invalid for SPIs).
+	bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
+	the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
+	the interrupt is wired to that CPU.  Only valid for PPI interrupts.
+	Also note that the configurability of PPI interrupts is IMPLEMENTATION
+	DEFINED and as such not guaranteed to be present (most SoC available
+	in 2014 seem to ignore the setting of this flag and use the hardware
+	default value).
+
+- reg : Specifies base physical address(s) and size of the GIC registers. The
+  first region is the GIC distributor register base and size. The 2nd region is
+  the GIC cpu interface register base and size.
+
+Optional
+- interrupts	: Interrupt source of the parent interrupt controller on
+  secondary GICs, or VGIC maintenance interrupt on primary GIC (see
+  below).
+
+- cpu-offset	: per-cpu offset within the distributor and cpu interface
+  regions, used when the GIC doesn't have banked registers. The offset is
+  cpu-offset * cpu-nr.
+
+- clocks        : List of phandle and clock-specific pairs, one for each entry
+  in clock-names.
+- clock-names   : List of names for the GIC clock input(s). Valid clock names
+  depend on the GIC variant:
+	"ic_clk" (for "arm,arm11mp-gic")
+	"PERIPHCLKEN" (for "arm,cortex-a15-gic")
+	"PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
+	"clk" (for "arm,gic-400" and "nvidia,tegra210")
+	"gclk" (for "arm,pl390")
+
+- power-domains : A phandle and PM domain specifier as defined by bindings of
+		  the power controller specified by phandle, used when the GIC
+		  is part of a Power or Clock Domain.
+
+
+Example:
+
+	intc: interrupt-controller@fff11000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		interrupt-controller;
+		reg = <0xfff11000 0x1000>,
+		      <0xfff10100 0x100>;
+	};
+
+
+* GIC virtualization extensions (VGIC)
+
+For ARM cores that support the virtualization extensions, additional
+properties must be described (they only exist if the GIC is the
+primary interrupt controller).
+
+Required properties:
+
+- reg : Additional regions specifying the base physical address and
+  size of the VGIC registers. The first additional region is the GIC
+  virtual interface control register base and size. The 2nd additional
+  region is the GIC virtual cpu interface register base and size.
+
+- interrupts : VGIC maintenance interrupt.
+
+Example:
+
+	interrupt-controller@2c001000 {
+		compatible = "arm,cortex-a15-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x2c001000 0x1000>,
+		      <0x2c002000 0x1000>,
+		      <0x2c004000 0x2000>,
+		      <0x2c006000 0x2000>;
+		interrupts = <1 9 0xf04>;
+	};
+
+
+* GICv2m extension for MSI/MSI-x support (Optional)
+
+Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
+This is enabled by specifying v2m sub-node(s).
+
+Required properties:
+
+- compatible	    : The value here should contain "arm,gic-v2m-frame".
+
+- msi-controller    : Identifies the node as an MSI controller.
+
+- reg		    : GICv2m MSI interface register base and size
+
+Optional properties:
+
+- arm,msi-base-spi  : When the MSI_TYPER register contains an incorrect
+			  value, this property should contain the SPI base of
+		      the MSI frame, overriding the HW value.
+
+- arm,msi-num-spis  : When the MSI_TYPER register contains an incorrect
+			  value, this property should contain the number of
+		      SPIs assigned to the frame, overriding the HW value.
+
+Example:
+
+	interrupt-controller@e1101000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		interrupt-controller;
+		interrupts = <1 8 0xf04>;
+		ranges = <0 0 0 0xe1100000 0 0x100000>;
+		reg = <0x0 0xe1110000 0 0x01000>,
+		      <0x0 0xe112f000 0 0x02000>,
+		      <0x0 0xe1140000 0 0x10000>,
+		      <0x0 0xe1160000 0 0x10000>;
+		v2m0: v2m@0x8000 {
+			compatible = "arm,gic-v2m-frame";
+			msi-controller;
+			reg = <0x0 0x80000 0 0x1000>;
+		};
+
+		....
+
+		v2mN: v2m@0x9000 {
+			compatible = "arm,gic-v2m-frame";
+			msi-controller;
+			reg = <0x0 0x90000 0 0x1000>;
+		};
+	};

qcom/Makefile

@@ -201,6 +201,11 @@ dtb-y += $(waipio_tuivm-dtb-y)
 endif
 endif
 
+sdxbaagha-dtb-$(CONFIG_ARCH_SDXBAAGHA) += sdxbaagha-rumi.dtb \
+	sdxbaagha-mtp.dtb \
+	sdxbaagha-cdp.dtb
+dtb-y += $(sdxbaagha-dtb-y)
+
 always-y        := $(dtb-y)
 subdir-y        := $(dts-dirs)
 clean-files     := *.dtb *.dtbo

qcom/sdxbaagha-cdp.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdxbaagha.dtsi"
+#include "sdxbaagha-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SDXBAAGHA CDP";
+	compatible = "qcom,sdxbaagha-cdp",
+		"qcom,sdxbaagha", "qcom,cdp";
+	qcom,board-id = <0x01 0>;
+};

qcom/sdxbaagha-cdp.dtsi

@@ -0,0 +1,2 @@
+&soc {
+};

qcom/sdxbaagha-mtp.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdxbaagha.dtsi"
+#include "sdxbaagha-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SDXBAAGHA MTP";
+	compatible = "qcom,sdxbaagha-mtp",
+		"qcom,sdxbaagha", "qcom,mtp";
+	qcom,board-id = <0x08 0>;
+};

qcom/sdxbaagha-mtp.dtsi

@@ -0,0 +1,2 @@
+&soc {
+};

qcom/sdxbaagha-pinctrl.dtsi

@@ -0,0 +1,12 @@
+&soc {
+	tlmm: pinctrl@f100000 {
+		compatible = "qcom,sdxbaagha-pinctrl";
+		reg = <0xf100000 0x300000>;
+		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&intc>;
+		#interrupt-cells = <2>;
+	};
+};

qcom/sdxbaagha-rumi.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdxbaagha.dtsi"
+#include "sdxbaagha-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SDXBAAGHA RUMI";
+	compatible = "qcom,sdxbaagha-rumi",
+		"qcom,sdxbaagha", "qcom,rumi";
+	qcom,board-id = <0x0F 0>;
+};

qcom/sdxbaagha-rumi.dtsi

@@ -0,0 +1,2 @@
+&soc {
+};

qcom/sdxbaagha.dtsi

@@ -0,0 +1,134 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	model = "Qualcomm Technologies, Inc. SDXBAAGHA";
+	compatible = "qcom,sdxbaagha";
+	qcom,msm-id = <570 0x10000>, <571 0x10000>;
+	interrupt-parent = <&intc>;
+
+	aliases { };
+
+	chosen { };
+
+	memory { device_type = "memory"; reg = <0 0>; };
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		peripheral2_mem: peripheral2_region@8fd00000 {
+			no-map;
+			reg = <0x8fd00000 0x140000>;
+			label = "peripheral2_mem";
+		};
+	};
+
+	cpus {
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+		};
+	};
+
+	soc: soc { };
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+	compatible = "simple-bus";
+
+	intc: interrupt-controller@17000000 {
+		compatible = "qcom,msm-qgic2";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x17000000 0x1000>,
+		      <0x17002000 0x1000>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 0xf08>,
+			<1 12 0xf08>,
+			<1 10 0xf08>,
+			<1 11 0xf08>;
+		clock-frequency = <19200000>;
+	};
+
+	timer@17020000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x17020000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@17021000 {
+			frame-number = <0>;
+			interrupts = <0 7 0x4>,
+				     <0 6 0x4>;
+			reg = <0x17021000 0x1000>,
+			      <0x17022000 0x1000>;
+		};
+
+		frame@17023000 {
+			frame-number = <1>;
+			interrupts = <0 8 0x4>;
+			reg = <0x17023000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17024000 {
+			frame-number = <2>;
+			interrupts = <0 9 0x4>;
+			reg = <0x17024000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17025000 {
+			frame-number = <3>;
+			interrupts = <0 10 0x4>;
+			reg = <0x17025000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17026000 {
+			frame-number = <4>;
+			interrupts = <0 11 0x4>;
+			reg = <0x17026000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17027000 {
+			frame-number = <5>;
+			interrupts = <0 12 0x4>;
+			reg = <0x17027000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17028000 {
+			frame-number = <6>;
+			interrupts = <0 13 0x4>;
+			reg = <0x17028000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@17029000 {
+			frame-number = <7>;
+			interrupts = <0 14 0x4>;
+			reg = <0x17029000 0x1000>;
+			status = "disabled";
+		};
+	};
+};
+
+#include "sdxbaagha-pinctrl.dtsi"