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ARM: dts: msm: Enable gfx smmu and config clks

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Enable gfx smmu, also config clks needed.

Change-Id: I6d0e27294d8f7533b77f173845c2f1841077c117
This commit is contained in:
Zhenhua Huang
2022-09-21 18:10:14 +08:00
parent eb36c5f076
commit 22e595cc91
1 changed files with 17 additions and 1 deletions
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18
qcom/msm-arm-smmu-ravelin.dtsi
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@@ -10,17 +10,33 @@
qcom,use-3-lvl-tables;
qcom,num-context-banks-override = <0x5>;
qcom,num-smr-override = <0x7>;
status = "disabled";
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
qcom,regulator-names = "vdd";
vdd-supply = <&gpu_cc_cx_gdsc>;
qcom,actlr =
/* All CBs of GFX: +15 deep PF */
<0x0 0x1FFF 0x328>;
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>;
clock-names =
"gpu_cc_cx_gmu",
"gpu_cc_hub_cx_int",
"gpu_cc_hlos1_vote_gpu_smmu",
"gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb";
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,