Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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Merge "ARM: dts: msm: Add PCIE_AXI, USB3_PRIM_AXI clock handle for NEO"

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qctecmdr
2022-05-09 00:55:50 -07:00
committed by Gerrit - the friendly Code Review server
parent 2a1cb39666 73d6a78f6b
commit 3376e7d461
1 changed files with 4 additions and 2 deletions
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6
qcom/neo.dtsi
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@@ -692,8 +692,7 @@
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "sleep_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, <GCC_DDRSS_PCIE_SF_CLK>,
protected-clocks = <GCC_DDRSS_PCIE_SF_CLK>,
<GCC_PCIE_0_AUX_CLK>, <GCC_PCIE_0_AUX_CLK_SRC>,
<GCC_PCIE_0_CFG_AHB_CLK>, <GCC_PCIE_0_MSTR_AXI_CLK>,
<GCC_PCIE_0_PHY_RCHNG_CLK>, <GCC_PCIE_0_PHY_RCHNG_CLK_SRC>,
@@ -1266,6 +1265,7 @@
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <1>;
clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
pcie_noc: interconnect@16c0000 {
@@ -1274,6 +1274,8 @@
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <1>;
clocks = <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
};
mmss_noc: interconnect@1740000 {