mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ARM: dts: msm: Add initial device tree for Diwali
Add initial device tree to support Diwali on RUMI platform. Change-Id: If2f516b6c07431ebf8d15ae74da08268455380a8
This commit is contained in:
Prateek Sood
committed by
Mukesh Ojha
Mukesh Ojha
parent
869576c8f3
commit
3571454907
@@ -89,6 +89,9 @@ SoCs:
|
||||
- WAIPIO
|
||||
compatible = "qcom,waipio", "qcom,waipiop"
|
||||
|
||||
- DIWALI
|
||||
compatible = "qcom,diwali"
|
||||
|
||||
Generic board variants:
|
||||
|
||||
- CDP device:
|
||||
@@ -249,3 +252,4 @@ compatible = "qcom,waipio-qrd"
|
||||
compatible = "qcom,waipiop-mtp"
|
||||
compatible = "qcom,waipiop-cdp"
|
||||
compatible = "qcom,waipiop-qrd"
|
||||
compatible = "qcom,diwali-rumi"
|
||||
|
||||
@@ -101,6 +101,14 @@ dtb-$(CONFIG_ARCH_WAIPIO) += waipio-rumi.dtb \
|
||||
waipio-qrd-pm8010.dtb
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
|
||||
dtbo-$(CONFIG_ARCH_DIWALI) += diwali-rumi-overlay.dtbo
|
||||
|
||||
diwali-rumi-overlay.dtbo-base := diwali.dtb
|
||||
else
|
||||
dtb-$(CONFIG_ARCH_DIWALI) += diwali-rumi.dtb
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
|
||||
dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo
|
||||
dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \
|
||||
|
||||
11
qcom/diwali-rumi-overlay.dts
Normal file
11
qcom/diwali-rumi-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "diwali-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Diwali RUMI";
|
||||
compatible = "qcom,diwali-rumi", "qcom,diwali", "qcom,rumi";
|
||||
qcom,msm-id = <506 0x10000>;
|
||||
qcom,board-id = <0x1000F 0>;
|
||||
};
|
||||
11
qcom/diwali-rumi.dts
Normal file
11
qcom/diwali-rumi.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/memreserve/ 0x90000000 0x00010000;
|
||||
|
||||
#include "diwali.dtsi"
|
||||
#include "diwali-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Diwali RUMI";
|
||||
compatible = "qcom,diwali-rumi", "qcom,diwali", "qcom,rumi";
|
||||
qcom,board-id = <0x1000F 0>;
|
||||
};
|
||||
14
qcom/diwali-rumi.dtsi
Normal file
14
qcom/diwali-rumi.dtsi
Normal file
@@ -0,0 +1,14 @@
|
||||
|
||||
&soc {
|
||||
timer {
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
|
||||
timer@17420000 {
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
|
||||
qcom,wdt@17410000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
9
qcom/diwali.dts
Normal file
9
qcom/diwali.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "diwali.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Diwali SoC";
|
||||
compatible = "qcom,diwali";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
266
qcom/diwali.dtsi
Normal file
266
qcom/diwali.dtsi
Normal file
@@ -0,0 +1,266 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Diwali";
|
||||
compatible = "qcom,diwali";
|
||||
qcom,msm-id = <506 0x10000>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen: chosen { };
|
||||
|
||||
memory { device_type = "memory"; reg = <0 0 0 0>; };
|
||||
|
||||
reserved_memory: reserved-memory { };
|
||||
|
||||
aliases { };
|
||||
|
||||
firmware: firmware { };
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
|
||||
L3_0: l3-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-level = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>; /* silver L2 sharing */
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_2>;
|
||||
L2_2: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_2>; /* silver L2 sharing */
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_4>;
|
||||
L2_4: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_5>;
|
||||
L2_5: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x600>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_6>;
|
||||
L2_6: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x700>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_7>;
|
||||
L2_7: l2-cache {
|
||||
compatible = "arm,arch-cache";
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU4>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU5>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&CPU6>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster2 {
|
||||
core0 {
|
||||
cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
};
|
||||
|
||||
&firmware {
|
||||
qcom_scm {
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
intc: interrupt-controller@17100000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x40000>;
|
||||
reg = <0x17100000 0x10000>, /* GICD */
|
||||
<0x17180000 0x200000>; /* GICR * 8 */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
wdog: qcom,wdt@17410000 {
|
||||
compatible = "qcom,msm-watchdog";
|
||||
reg = <0x17410000 0x1000>;
|
||||
reg-names = "wdt-base";
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
memtimer: timer@17420000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0x17420000 0x1000>;
|
||||
clock-frequency = <19200000>;
|
||||
|
||||
frame@17421000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17421000 0x1000>,
|
||||
<0x17422000 0x1000>;
|
||||
};
|
||||
|
||||
frame@17423000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17423000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17425000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17425000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17427000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17427000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@17429000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x17429000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@1742b000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x1742b000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@1742d000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x1742d000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user