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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
Merge "ARM: dts: msm: Add MHI nodes for waipio endpoint"
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41
qcom/waipio-mhi.dtsi
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41
qcom/waipio-mhi.dtsi
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@@ -0,0 +1,41 @@
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&pcie1 {
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qcom,no-l1ss-supported;
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};
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&pcie1_rp {
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#address-cells = <5>;
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#size-cells = <0>;
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mhi_0: qcom,mhi@0 {
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reg = <0 0 0 0 0 >;
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pci-ids = "17cb:0111";
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/* controller specific configuration */
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qcom,iommu-group = <&mhi_0_iommu_group>;
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/* mhi bus specific settings */
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mhi,max-channels = <2>;
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mhi,timeout = <2000>;
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mhi,name = "sxr";
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#address-cells = <1>;
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#size-cells = <1>;
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interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
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interconnect-names = "pcie_to_ddr";
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qcom,mhi-bus-bw-cfg = <0 0>, /* no vote */
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<250000 0>, /* avg bw / AB: 2 GBps, peak bw / IB: no vote */
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<500000 0>, /* avg bw / AB: 4 GBps, peak bw / IB: no vote */
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<1000000 0>, /* avg bw / AB: 8 GBps, peak bw / IB: no vote */
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<2000000 0>; /* avg bw / AB: 16 GBps, peak bw / IB: no vote */
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mhi_0_iommu_group: mhi_0_iommu_group {
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qcom,iommu-dma-addr-pool = <0x20000000 0x1fffffff>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-pagetable = "coherent";
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};
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};
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};
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@@ -3651,6 +3651,7 @@
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#include "waipio-debug.dtsi"
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#include "waipio-eva.dtsi"
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#include "waipio-pcie.dtsi"
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#include "waipio-mhi.dtsi"
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#include "msm-rdbg.dtsi"
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#include "waipio-gpu.dtsi"
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#include "waipio-thermal.dtsi"
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