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ARM: dts: msm: Add QUPv3 UART console node for anorak

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Enable console support on anorak

Change-Id: I9a75d83ff55580b33981d2fb28fcfe3c01c292cb
This commit is contained in:
Yatish Kumar Singh
2022-05-02 15:06:00 +05:30
parent 00fab1a008
commit 3e9d32505f
4 changed files with 75 additions and 0 deletions
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26
qcom/anorak-pinctrl.dtsi
View File

@@ -1,3 +1,29 @@
&tlmm {
qupv3_se6_2uart_pins: qupv3_se6_2uart_pins {
qupv3_se6_2uart_active: qupv3_se6_2uart_active {
mux {
pins = "gpio156", "gpio157";
function = "qup0_se6";
};
config {
pins = "gpio156", "gpio157";
drive-strength= <2>;
bias-disable;
};
};
qupv3_se6_2uart_sleep: qupv3_se6_2uart_sleep {
mux {
pins = "gpio156", "gpio157";
function = "gpio";
};
config {
pins = "gpio156", "gpio157";
drive-strength = <2>;
bias-pull-down;
};
};
};
};

39
qcom/anorak-qupv3.dtsi Normal file
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@@ -0,0 +1,39 @@
&soc {
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0x9c0000 0x2000>;
qcom,msm-bus,num-paths = <3>;
interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
/*
* iommus = <&apps_smmu 0x5a3 0x0>;
* qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
* qcom,iommu-geometry = <0x40000000 0x10000000>;
* qcom,iommu-dma = "fastmap";
* dma-coherent;
*/
status = "ok";
};
/* Debug UART Instance */
qupv3_se6_2uart: qcom,qup_uart@998000 {
compatible = "qcom,msm-geni-console";
reg = <0x998000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_2uart_active>;
pinctrl-1 = <&qupv3_se6_2uart_sleep>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
};

4
qcom/anorak-rumi.dtsi
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@@ -89,6 +89,10 @@
};
&qupv3_se6_2uart {
qcom,rumi_platform;
};
&gcc {
clocks = <&bi_tcxo>, <&sleep_clk>,
<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,

6
qcom/anorak.dtsi
View File

@@ -31,6 +31,7 @@
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
serial0 = &qupv3_se6_2uart;
};
cpus {
@@ -844,8 +845,13 @@
};
};
#include "anorak-qupv3.dtsi"
#include "diwali-gdsc.dtsi"
&qupv3_se6_2uart {
status = "ok";
};
&cam_cc_bps_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";