mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
Merge "ARM: dts: msm: Add LPM support for sm8150"
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qctecmdr
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Gerrit - the friendly Code Review server
commit
3ecf6cf9fb
@@ -12,6 +12,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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ufs_dev_reset_assert: ufs_dev_reset_assert {
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config {
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123
qcom/sm8150-pm.dtsi
Normal file
123
qcom/sm8150-pm.dtsi
Normal file
@@ -0,0 +1,123 @@
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&soc {
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qcom,lpm-levels {
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compatible = "qcom,lpm-levels";
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,pm-cluster@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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idle-state-name = "L3";
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qcom,clstr-tmr-add = <1000>;
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qcom,psci-mode-shift = <4>;
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qcom,psci-mode-mask = <0xfff>;
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CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */
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reg = <0>;
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compatible = "arm,idle-state";
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idle-state-name = "l3-wfi";
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entry-latency-us = <48>;
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exit-latency-us = <51>;
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min-residency-us = <99>;
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arm,psci-suspend-param = <0x10>;
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qcom,psci-mode = <0x1>;
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};
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LLCC_OFF: qcom,pm-cluster-level@1 { /* AOSS sleep */
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reg = <1>;
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compatible = "arm,idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <3263>;
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exit-latency-us = <6562>;
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min-residency-us = <9987>;
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arm,psci-suspend-param = <0xc240>;
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qcom,psci-mode = <0xc24>;
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qcom,is-reset;
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qcom,notify-rpm;
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qcom,min-child-idx = <1>;
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};
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qcom,pm-cpu@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,psci-mode-shift = <0>;
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qcom,psci-mode-mask = <0xf>;
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qcom,ref-stddev = <500>;
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qcom,tmr-add = <1000>;
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qcom,ref-premature-cnt = <1>;
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qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
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SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */
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reg = <0>;
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compatible = "arm,idle-state";
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idle-state-name = "wfi";
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entry-latency-us = <57>;
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exit-latency-us = <43>;
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min-residency-us = <100>;
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arm,psci-suspend-param = <0x1>;
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qcom,psci-cpu-mode = <0x1>;
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};
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SLVR_RAIL_OFF: qcom,pm-cpu-level@1 { /* C4 */
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reg = <1>;
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <355>;
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exit-latency-us = <909>;
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min-residency-us = <3934>;
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arm,psci-suspend-param = <0x40000004>;
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qcom,psci-cpu-mode = <0x4>;
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local-timer-stop;
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qcom,is-reset;
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qcom,use-broadcast-timer;
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};
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};
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qcom,pm-cpu@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,psci-mode-shift = <0>;
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qcom,psci-mode-mask = <0xf>;
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qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
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GOLD_WFI: qcom,pm-cpu-level@0 { /* C1 */
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reg = <0>;
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compatible = "arm,idle-state";
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idle-state-name = "wfi";
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entry-latency-us = <57>;
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exit-latency-us = <43>;
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min-residency-us = <83>;
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arm,psci-suspend-param = <0x1>;
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qcom,psci-cpu-mode = <0x1>;
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};
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GOLD_RAIL_OFF: qcom,pm-cpu-level@1 { /* C4 */
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reg = <1>;
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <2411>;
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exit-latency-us = <1461>;
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min-residency-us = <4488>;
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arm,psci-suspend-param = <0x40000004>;
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qcom,psci-cpu-mode = <0x4>;
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local-timer-stop;
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qcom,is-reset;
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qcom,use-broadcast-timer;
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};
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};
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};
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};
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rpmh-master-stats@b221200 {
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compatible = "qcom,rpmh-master-stats-v1";
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reg = <0xb221200 0x60>;
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};
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soc-sleep-stats@c3f0000 {
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compatible = "qcom,rpmh-sleep-stats";
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reg = <0xc3f0000 0x400>;
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};
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};
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@@ -26,6 +26,7 @@
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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@@ -62,6 +63,7 @@
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_1>;
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@@ -92,6 +94,7 @@
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_2>;
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@@ -122,6 +125,7 @@
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_3>;
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@@ -152,6 +156,7 @@
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_4>;
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@@ -191,6 +196,7 @@
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_5>;
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@@ -230,6 +236,7 @@
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_6>;
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@@ -269,6 +276,7 @@
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_7>;
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@@ -579,10 +587,11 @@
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interrupt-parent = <&intc>;
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};
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pdc: interrupt-controller@0xb220000 {
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compatible = "qcom,pdc-sm8150";
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reg = <0xb220000 0x400>;
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#interrupt-cells = <3>;
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8150-pdc";
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reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
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qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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@@ -673,9 +682,9 @@
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<CONTROL_TCS 0>;
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<SLEEP_TCS 3>,
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<WAKE_TCS 3>,
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<CONTROL_TCS 1>;
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rpmhcc: clock-controller {
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compatible = "qcom,sm8150-rpmh-clk";
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@@ -684,6 +693,25 @@
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clocks = <&xo_board>;
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status = "okay";
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};
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system_pm {
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compatible = "qcom,system-pm";
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};
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};
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disp_rsc: rsc@af20000 {
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label = "disp_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0xaf20000 0x10000>;
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reg-names = "drv-0";
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0x1c00>;
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qcom,drv-id = <0>;
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qcom,tcs-config = <SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<ACTIVE_TCS 2>,
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<CONTROL_TCS 0>;
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};
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gcc: clock-controller@100000 {
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@@ -723,3 +751,4 @@
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#include "sm8150-pinctrl.dtsi"
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#include "sm8150-regulator.dtsi"
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#include "sm8150-pm.dtsi"
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