mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
Merge "ARM: dts: msm: Add initial device tree for Anorak"
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qctecmdr
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Gerrit - the friendly Code Review server
commit
3ee230a731
@@ -101,6 +101,9 @@ SoCs:
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- PARROT
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compatible = "qcom,parrot"
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- ANORAK
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compatible = "qcom,anorak"
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Generic board variants:
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- CDP device:
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@@ -283,3 +286,5 @@ compatible = "qcom,diwalip-qrd"
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compatible = "qcom,diwalip-atp"
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compatible = "qcom,neo-rumi"
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compatible = "qcom,parrot-rumi"
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compatible = "qcom,anorak-rumi"
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compatible = "qcom,anorak-idp"
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@@ -344,6 +344,13 @@ dtb-$(CONFIG_ARCH_SM8150) += sm8150-cdp.dtb \
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endif
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endif
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ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
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dtbo-$(CONFIG_ARCH_ANORAK) += anorak-rumi-overlay.dtbo
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anorak-rumi-overlay.dtbo-base := anorak.dtb
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else
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dtb-$(CONFIG_ARCH_ANORAK) += anorak-rumi.dtb
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endif
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ifeq ($(CONFIG_ARCH_LAHAINA), y)
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ifeq ($(CONFIG_ARCH_QTI_VM), y)
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dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \
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12
qcom/anorak-rumi-overlay.dts
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12
qcom/anorak-rumi-overlay.dts
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@@ -0,0 +1,12 @@
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/dts-v1/;
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/plugin/;
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#include "anorak.dtsi"
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#include "anorak-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Anorak RUMI";
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compatible = "qcom,anorak-rumi", "qcom,anorak", "qcom,rumi";
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qcom,msm-id = <549 0x10000>;
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qcom,board-id = <0xF 0x0>;
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};
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11
qcom/anorak-rumi.dts
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11
qcom/anorak-rumi.dts
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@@ -0,0 +1,11 @@
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/dts-v1/;
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/memreserve/ 0x90000000 0x00010000;
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#include "anorak.dtsi"
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#include "anorak-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Anorak RUMI";
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compatible = "qcom,anorak-rumi", "qcom,anorak", "qcom,rumi";
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qcom,board-id = <0xF 0x0>;
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};
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15
qcom/anorak-rumi.dtsi
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15
qcom/anorak-rumi.dtsi
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@@ -0,0 +1,15 @@
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&chosen {
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bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
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};
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&arch_timer {
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clock-frequency = <500000>;
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};
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&memtimer {
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clock-frequency = <500000>;
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};
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&soc {
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};
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9
qcom/anorak.dts
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9
qcom/anorak.dts
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@@ -0,0 +1,9 @@
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/dts-v1/;
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#include "anorak.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Anorak SoC";
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compatible = "qcom,anorak";
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qcom,board-id = <0 0>;
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};
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231
qcom/anorak.dtsi
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231
qcom/anorak.dtsi
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@@ -0,0 +1,231 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. Anorak";
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compatible = "qcom,anorak";
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qcom,msm-id = <549 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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chosen: chosen { };
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aliases { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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core2 {
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cpu = <&CPU4>;
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};
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core3 {
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cpu = <&CPU5>;
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};
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};
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17200000 0x10000>, /* GICD */
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<0x17260000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17420000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17420000 0x1000>;
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clock-frequency = <19200000>;
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frame@17421000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17421000 0x1000>,
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<0x17422000 0x1000>;
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};
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frame@17423000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17423000 0x1000>;
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status = "disabled";
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};
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frame@17425000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17425000 0x1000>;
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status = "disabled";
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};
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frame@17427000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17427000 0x1000>;
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status = "disabled";
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};
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frame@17429000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17429000 0x1000>;
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status = "disabled";
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};
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frame@1742b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742b000 0x1000>;
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status = "disabled";
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};
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frame@1742d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742d000 0x1000>;
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status = "disabled";
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};
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};
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};
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