Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: Add NFC device node for ravelin (SM4450)

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Device node changes required on ravelin (SM4450), describing
the GPIO configuration for Nfc controller chip.

Modified corresponding Nfc device node
for ATP, IDP & QRD platforms.

Change-Id: I5682fada78c9573e0f8697b2da1d62b855465404
This commit is contained in:
Amruth Naga
2022-11-17 21:33:09 +05:30
committed by Gerrit - the friendly Code Review server
parent cd2547e9e3
commit 4ce55200a9
4 changed files with 131 additions and 0 deletions
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24
qcom/ravelin-atp.dtsi
View File

@@ -64,3 +64,27 @@
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&qupv3_se0_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 9 0x00>;
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L21B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};

24
qcom/ravelin-idp.dtsi
View File

@@ -107,3 +107,27 @@
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&qupv3_se0_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 9 0x00>;
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L21B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};

59
qcom/ravelin-pinctrl.dtsi
View File

@@ -1312,5 +1312,64 @@
};
};
};
nfc {
nfc_int_active: nfc_int_active {
/* active state */
mux {
/* NFC Read Interrupt */
pins = "gpio9";
function = "gpio";
};
config {
pins = "gpio9";
drive-strength = <2>; /* 2 MA */
bias-pull-down;
};
};
nfc_int_suspend: nfc_int_suspend {
/* sleep state */
mux {
/* NFC Read Interrupt */
pins = "gpio9";
function = "gpio";
};
config {
pins = "gpio9";
drive-strength = <2>; /* 2 MA */
bias-pull-down;
};
};
nfc_enable_active: nfc_enable_active {
mux {
/* Enable, Firmware and Clock request gpios */
pins = "gpio6", "gpio8", "gpio7";
function = "gpio";
};
config {
pins = "gpio6", "gpio8", "gpio7";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
nfc_enable_suspend: nfc_enable_suspend {
mux {
pins = "gpio6", "gpio8", "gpio7";
function = "gpio";
};
config {
pins = "gpio6", "gpio8", "gpio7";
drive-strength = <2>; /* 2 MA */
bias-disable;
};
};
};
};
};

24
qcom/ravelin-qrd.dtsi
View File

@@ -64,3 +64,27 @@
cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
};
&qupv3_se0_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 9 0x00>;
qcom,sn-ven = <&tlmm 6 0x00>;
qcom,sn-firm = <&tlmm 8 0x00>;
qcom,sn-clkreq = <&tlmm 7 0x00>;
qcom,sn-vdd-1p8-supply = <&L21B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <9 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};