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ARM: dts: qcom: Add SPU related nodes to waipio
Needed for SPU pil on waipio. Change-Id: Ied93685b6987033cfe9a4373680f0af1f56c9562
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Liron Daniel
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bindings/remoteproc/qcom,spss.txt
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59
bindings/remoteproc/qcom,spss.txt
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@@ -0,0 +1,59 @@
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Qualcomm Technologies, Inc. SPSS Peripheral Image Loader
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This document defines the binding for a component that loads and boots firmware
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on the QTI Secure Processor.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be one of:
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"qcom,waipio-spss-pas"
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- reg:
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Usage: required
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Value type: <prop-encoded>
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Definition: pairs of physical base addresses and region sizes of memory
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mapped registers
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- reg-names:
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Usage: required
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Value type: <stringlist>
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Definition: names of the registers defined by the 'reg' property above
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- interrupts:
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Usage: required
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Value type: <prop-encoded>
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Definition: generic interrupt
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the xo clock and optionally aggre2 clock to be
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held on behalf of the booting Hexagon core
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "xo" and optionally include "aggre2"
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- cx-supply:
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Usage: required
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Value type: <phandle>
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Definition: reference to the regulator to be held on behalf of the
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booting Hexagon core
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- px-supply:
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Usage: required
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Value type: <phandle>
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Definition: reference to the px regulator to be held on behalf of the
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booting Hexagon core
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- memory-region:
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Usage: required
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Value type: <phandle>
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Definition: reference to the reserved-memory for the ADSP
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= SUBNODES
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The adsp node may have an subnode named "glink-edge" that describes the
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communication edge, channels and devices related to the SPSS.
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@@ -1138,6 +1138,95 @@
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};
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};
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/* PIL spss node - for loading Secure Processor */
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spss_pas: remoteproc-spss@1880000 {
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compatible = "qcom,waipio-spss-pas";
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ranges;
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reg = <0x188101c 0x4>,
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<0x1881024 0x4>,
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<0x1881028 0x4>,
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<0x188103c 0x4>,
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<0x1882014 0x4>;
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reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
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"sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";
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interrupts = <0 352 1>;
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cx-supply = <&VDD_CX_LEVEL>;
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cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
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px-supply = <&VDD_MXA_LEVEL>;
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px-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
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clocks = <&clock_rpmh RPMH_CXO_CLK>;
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clock-names = "xo";
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qcom,proxy-clock-names = "xo";
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status = "ok";
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memory-region = <&spss_region_mem>;
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qcom,spss-scsr-bits = <24 25>;
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qcom,extra-size = <4096>;
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interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
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interconnect-names = "crypto_ddr";
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glink-edge {
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qcom,remote-pid = <8>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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mbox-names = "spss_spss";
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_SPSS
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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reg = <0x1885008 0x8>,
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<0x1885010 0x4>;
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reg-names = "qcom,spss-addr",
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"qcom,spss-size";
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label = "spss";
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qcom,glink-label = "spss";
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};
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};
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qcom,spcom {
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compatible = "qcom,spcom";
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qcom,rproc-handle = <&spss_pas>;
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qcom,boot-enabled;
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/* predefined channels, remote side is server */
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qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
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/* sp2soc rmb shared register physical address and bmsk */
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qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
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qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
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qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
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/* soc2sp rmb shared register physical address */
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qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
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qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
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status = "ok";
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};
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spss_utils: qcom,spss_utils {
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compatible = "qcom,spss-utils";
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/* spss fuses physical address */
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qcom,rproc-handle = <&spss_pas>;
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qcom,spss-fuse1-addr = <0x221C22EC>;
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qcom,spss-fuse1-bit = <8>;
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qcom,spss-fuse2-addr = <0x221C22EC>;
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qcom,spss-fuse2-bit = <7>;
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qcom,spss-fuse3-addr = <0x221C2238>; // IAR_FEATURE_ENABLED fuse
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qcom,spss-fuse3-bit = <10>;
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qcom,spss-fuse4-addr = <0x221C22EC>; // IAR_STATE fuse
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qcom,spss-fuse4-bit = <21>; // 0x221C22EC bits 21-23
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qcom,spss-dev-firmware-name = "spss1d.mdt"; /* 8 chars max */
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qcom,spss-test-firmware-name = "spss1t.mdt"; /* 8 chars max */
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qcom,spss-prod-firmware-name = "spss1p.mdt"; /* 8 chars max */
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qcom,spss-debug-reg-addr = <0x01886020>;
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qcom,spss-emul-type-reg-addr = <0x01fc8004>;
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pil-mem = <&spss_region_mem>;
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qcom,pil-size = <0x0F0000>; // padding to 960KB
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status = "ok";
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};
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cache-controller@19200000 {
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compatible = "qcom,waipio-llcc", "qcom,llcc-v21";
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reg = <0x19200000 0x580000> , <0x19A00000 0x80000>;
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