Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees synced 2026-02-01 08:51:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge "dt-bindings: Document child nodes for iommu-debug-test devices"

Browse Source
This commit is contained in:
qctecmdr
2020-07-23 19:13:18 -07:00
committed by Gerrit - the friendly Code Review server
parent 6c34952fd0 ad214af3c7
commit 78d738ba0b
4 changed files with 158 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
bindings/iommu/iommu-debug-test.yaml
View File

@@ -18,14 +18,16 @@ properties:
items:
- const: iommu-debug-test
iommus:
minItems: 1
items:
- description: IOMMU specifier with a SID and an SMR mask
description:
The SID in the IOMMU specifier is a placeholder so that the SMMU driver
can recognize the node. Our test uses ATOS, which doesn't use SIDs anyway,
so using a dummy value is ok.
child nodes:
compatible: : iommu-debug-usecase
iommus:
minItems: 1
items:
- description: IOMMU specifier with a SID and an SMR mask
description:
The SID in the IOMMU specifier is a placeholder so that the SMMU driver
can recognize the node. Our test uses ATOS, which doesn't use SIDs anyway,
so using a dummy value is ok.
required:
- compatible
@@ -35,5 +37,8 @@ examples:
- |
iommu_test_device {
compatible = "iommu-debug-test";
iommus = <&cpp_fd_smmu 42>;
basic_usecase {
compatible = "iommu-debug-usecase";
iommus = <&cpp_fd_smmu 42>;
}
};

89
qcom/msm-arm-smmu-sdxlemur.dtsi Normal file
View File

@@ -0,0 +1,89 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
apps_smmu: apps-smmu@15000000 {
compatible = "qcom,qsmmu-v500";
reg = <0x15000000 0x40000>,
<0x15042000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&system_noc MASTER_APPSS_PROC
&mem_noc SLAVE_IMEM_CFG>;
qcom,active-only;
periph_tbu: periph_tbu@15045000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x15045000 0x1000>,
<0x15042200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
interconnects = <&system_noc MASTER_APPSS_PROC
&mem_noc SLAVE_IMEM_CFG>;
qcom,active-only;
};
ipa_tbu: ipa_tbu@15049000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x15049000 0x1000>,
<0x15042208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
interconnects = <&system_noc MASTER_APPSS_PROC
&mem_noc SLAVE_IMEM_CFG>;
qcom,active-only;
};
};
apps_iommu_test_device {
compatible = "iommu-debug-test";
iommus = <&apps_smmu 0x100 0>;
qcom,iommu-dma = "disabled";
};
apps_iommu_coherent_test_device {
compatible = "iommu-debug-test";
iommus = <&apps_smmu 0x101 0>;
qcom,iommu-dma = "disabled";
dma-coherent;
};
};

15
qcom/sdxlemur-ion.dtsi Normal file
View File

@@ -0,0 +1,15 @@
#include <dt-bindings/arm/msm/msm_ion_ids.h>
&soc {
qcom,ion {
compatible = "qcom,msm-ion";
#address-cells = <1>;
#size-cells = <0>;
system_heap: qcom,ion-heap@25 {
reg = <ION_SYSTEM_HEAP_ID>;
qcom,ion-heap-type = "MSM_SYSTEM";
};
};
};

44
qcom/sdxlemur.dtsi
View File

@@ -21,7 +21,7 @@
memory { device_type = "memory"; reg = <0 0>; };
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -32,10 +32,14 @@
reg = <0x8fe20000 0x20000>;
};
peripheral2_mem: peripheral2_region@8fd00000 {
mpss_adsp_mem: mpss_adsp_region@90800000 {
no-map;
reg = <0x8fd00000 0x140000>;
label = "peripheral2_mem";
reg = <0x90800000 0x10000000>;
};
tz_mem: tz_mem_region@8ff00000 {
no-map;
reg = <0x8ff00000 0x600000>;
};
smem_mem: smem_region@8fe40000 {
@@ -43,6 +47,36 @@
reg = <0x8fe40000 0xc0000>;
label = "smem_mem";
};
peripheral_mem: peripheral_region@8fd00000 {
no-map;
reg = <0x8fd00000 0x140000>;
};
/*
* The exact size of this region may vary based on DDR size.
* 0x100000 will be valid for all DDR sizes at the cost of
* slightly reducing the memory available for HLOS.
*/
peripheral_mem2: peripheral_region2@8fb00000 {
no-map;
reg = <0x8fb00000 0x100000>;
};
mpss_dsm: mpss_dsm_region@8c400000 {
no-map;
reg = <0x8c400000 0x3200000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x00000000 0xffffffff>;
reusable;
alignment = <0x400000>;
size = <0xC00000>;
linux,cma-default;
};
};
cpus {
@@ -507,5 +541,7 @@
#include "sdxlemur-pinctrl.dtsi"
#include "sdxlemur-stub-regulator.dtsi"
#include "msm-arm-smmu-sdxlemur.dtsi"
#include "sdxlemur-ion.dtsi"
#include "sdxlemur-usb.dtsi"
#include "sdxlemur-pm.dtsi"