mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ARM: dts: msm: Add anorak smmu regulator and icc votes
Add regulator and icc votes for TBUs in anorak smmu. Change-Id: I6e20f73deaefffebe135ca002562373966b06c2f
This commit is contained in:
@@ -204,6 +204,11 @@
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/* For compute +15 deep PF */
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<0x961 0x27 0x303>;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_TCU>;
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qcom,active-only;
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anoc_1_tbu: anoc_1_tbu@151c9000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x151c9000 0x1000>,
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@@ -211,6 +216,9 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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qcom,micro-idle;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,active-only;
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qcom,iova-width = <36>;
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};
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@@ -221,6 +229,9 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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qcom,micro-idle;
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_IMEM_CFG>;
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qcom,active-only;
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qcom,iova-width = <36>;
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};
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@@ -231,6 +242,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
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interconnects = <&mmss_noc MASTER_CAMNOC_SF
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -241,6 +257,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0xc00 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc>;
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interconnects = <&mmss_noc MASTER_CAMNOC_SF
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -251,6 +272,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1000 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
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interconnects = <&mmss_noc MASTER_MDP0
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -261,6 +287,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1400 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
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interconnects = <&mmss_noc MASTER_MDP1
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -271,6 +302,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1800 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf2_gdsc>;
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interconnects = <&mmss_noc MASTER_MDP_CORE1_0
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -281,6 +317,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x1c00 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf3_gdsc>;
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interconnects = <&mmss_noc MASTER_MDP_CORE1_1
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -291,6 +332,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2000 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>;
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interconnects = <&nsp_noc MASTER_CDSP_PROC
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -301,6 +347,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2400 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_turing_mmu_tbu1_gdsc>;
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interconnects = <&nsp_noc MASTER_CDSP_PROC
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -311,6 +362,9 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2800 0x400>;
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qcom,micro-idle;
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interconnects = <&lpass_ag_noc MASTER_LPASS_PROC
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -321,6 +375,9 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x2c00 0x400>;
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qcom,micro-idle;
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interconnects = <&pcie_noc MASTER_PCIE_0
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <36>;
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};
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@@ -331,6 +388,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x3000 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf4_gdsc>;
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interconnects = <&mmss_noc MASTER_CAMNOC_HF
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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@@ -341,6 +403,11 @@
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x3400 0x400>;
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qcom,micro-idle;
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qcom,regulator-names = "vdd";
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vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf5_gdsc>;
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interconnects = <&mmss_noc MASTER_CAMNOC_HF
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&mc_virt SLAVE_EBI1>;
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qcom,active-only;
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qcom,iova-width = <32>;
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};
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};
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