Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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Revert "ARM: dts: msm: Add USB CSR clock entry on Lahaina"

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This reverts commit b92c3f5e10.

Change-Id: I51e9650ee26b7a6cdc9ff881174521f5ed246dc4
This commit is contained in:
Mayank Rana
2020-08-24 20:52:38 -07:00
committed by Gerrit - the friendly Code Review server
parent 540e981f5e
commit 7fdda6ba7b
1 changed files with 4 additions and 6 deletions
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10
qcom/lahaina-usb.dtsi
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@@ -29,10 +29,9 @@
<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&clock_gcc GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON>;
<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "core_csr_clk";
"utmi_clk", "sleep_clk";
resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
@@ -365,10 +364,9 @@
<&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&clock_gcc GCC_USB30_SEC_SLEEP_CLK>,
<&clock_gcc GCC_USB3_SEC_CLKREF_EN>,
<&clock_gcc GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON>;
<&clock_gcc GCC_USB3_SEC_CLKREF_EN>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "xo", "core_csr_clk";
"utmi_clk", "sleep_clk", "xo";
resets = <&clock_gcc GCC_USB30_SEC_BCR>;
reset-names = "core_reset";