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bindings: clock: Add support for CAPE clock controllers

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Add the GCC, GPUCC, CAMCC, DISPCC, VIDEOCC clock controller
bindings for CAPE device.

Change-Id: I298a3b553950d0f8b0be72efca772d2f7702ccd8
This commit is contained in:
Taniya Das
2021-09-30 06:13:23 +05:30
parent 56eb6f100a
commit 844ff45065
5 changed files with 5 additions and 0 deletions
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1
bindings/clock/qcom,camcc.txt
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@@ -10,6 +10,7 @@ Required properties :
"qcom,waipio-camcc"
"qcom,waipio-camcc-v2"
"qcom,diwali-camcc"
"qcom,cape-camcc"
- reg : shall contain base register location and length.
- #clock-cells : from common clock binding, shall contain 1.
- #reset-cells : from common reset binding, shall contain 1.

1
bindings/clock/qcom,dispcc.txt
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@@ -11,6 +11,7 @@ Required properties :
"qcom,holi-dispcc"
"qcom,waipio-dispcc"
"qcom,diwali-dispcc"
"qcom,cape-dispcc"
- reg : shall contain base register location and length.
- #clock-cells : from common clock binding, shall contain 1.

1
bindings/clock/qcom,gcc.txt
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@@ -33,6 +33,7 @@ Required properties :
"qcom,sdxlemur-gcc"
"qcom,waipio-gcc"
"qcom,diwali-gcc"
"qcom,cape-gcc"
- reg : shall contain base register location and length
- vdd_cx-supply: The vdd_cx logic rail supply.

1
bindings/clock/qcom,gpucc.txt
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@@ -9,6 +9,7 @@ Required properties :
"qcom,waipio-gpucc",
"qcom,waipio-gpucc-v2",
"qcom,diwali-gpucc".
"qcom,cape-gpucc",
- reg: shall contain base register offset and size.
- reg-names: names of registers listed in the same order as in the reg property.
Must contain "cc_base".

1
bindings/clock/qcom,videocc.txt
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@@ -9,6 +9,7 @@ Required properties :
"qcom,shima-videocc"
"qcom,waipio-videocc"
"qcom,diwali-videocc"
"qcom,cape-videocc"
- reg : shall contain base register location and length
- #clock-cells : from common clock binding, shall contain 1.