Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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Merge "ARM: dts: msm: Add next-level-cache for core 4 on Ravelin"

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qctecmdr
2022-11-02 15:16:08 -07:00
committed by Gerrit - the friendly Code Review server
parent ca3e702fd3 29f936c130
commit 8f368613f4
1 changed files with 1 additions and 0 deletions
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qcom/ravelin.dtsi
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@@ -135,6 +135,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_4: l2-cache {