Merge "ARM: dts: msm: Add iommu device for waipio-vm"

bindings/iommu/arm,smmu.txt

@@ -20,6 +20,7 @@ conditions.
                         "qcom,qsmmu-v500"
                         "qcom,adreno-smmu"
                         "qcom,smmu-v2"
+			"qcom,virt-smmu"
 
                   depending on the particular implementation and/or the
                   version of the architecture implemented.
@@ -33,6 +34,12 @@ conditions.
                   as below, SoC-specific compatibles:
                   "qcom,sdm845-smmu-500", "arm,mmu-500"
 
+		  "qcom,virt-smmu" is a subtype of "qcom,qsmmu-v500" which
+		  only supports access to the set of registers required by
+		  the arm specificiation. None of the additional registers
+		  normally present in qcom,qsmmu-v500 are supported
+		  currently.
+
 - reg           : Base address and size of the SMMU.
 
 - reg-names	: For the "qcom,qsmmu-v500" device "tcu-base" is expected.

qcom/msm-arm-smmu-waipio-vm.dtsi

@@ -0,0 +1,31 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	vm-config {
+		vdevices {
+			vsmmu@15000000 {
+				vdevice-type = "vsmmu-v2";
+				smmu-handle = <0x15000000>;
+				num-cbs = <0x2>;
+				num-smrs = <0x3>;
+				patch = "/soc/apps-smmu@15000000";
+			};
+		};
+	};
+};
+
+&soc {
+	apps_smmu: apps-smmu@15000000 {
+		/*
+		 * reg, #global-interrupts & interrupts  properties will
+		 * be added dynamically by bootloader.
+		 */
+		compatible = "qcom,qsmmu-v500", "qcom,virt-smmu";
+		#iommu-cells = <2>;
+		qcom,use-3-lvl-tables;
+		dma-coherent;
+		qcom,actlr =
+			<0x2803 0x0400 0x00000001>,
+			<0x2804 0x0402 0x00000001>;
+	};
+};

qcom/waipio-vm.dtsi

@@ -369,3 +369,4 @@
 };
 
 #include "waipio-vm-dma-heaps.dtsi"
+#include "msm-arm-smmu-waipio-vm.dtsi"