Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: enable rimps, scmi node

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Enable rimps, scmi  and sram node in
anorak.

Change-Id: I1b9ec85ec9cb8bc72945bd2f3953c34cb183fd22
This commit is contained in:
Shivnandan Kumar
2022-10-20 10:39:22 +05:30
parent 3307d1f276
commit a6bcbbe573
1 changed files with 52 additions and 0 deletions
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52
qcom/anorak.dtsi
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@@ -274,6 +274,19 @@
soc: soc { };
sram: sram@17D09100 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "mmio-sram";
reg = <0x0 0x17D09100 0x0 0x200>;
ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "arm,scp-shmem";
reg = <0x0 0x0 0x0 0x200>;
};
};
firmware: firmware { };
};
@@ -1291,6 +1304,8 @@
qcom_pmu: qcom,pmu {
compatible = "qcom,pmu";
reg = < 0x17D09300 0x300>;
reg-names = "pmu-base";
qcom,pmu-events-tbl =
< 0x0008 0x3F 0xFF 0x02 >,
< 0x0011 0x3F 0xFF 0x00 >,
@@ -1622,6 +1637,43 @@
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
};
rimps: qcom,rimps@17400000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,rimps";
reg = <0x17400000 0x10>,
<0x17d90000 0x2000>;
#mbox-cells = <1>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
scmi: qcom,scmi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,scmi";
mboxes = <&rimps 0>;
mbox-names = "tx";
shmem = <&cpu_scp_lpri>;
scmi_plh: protocol@81 {
reg = <0x81>;
#clock-cells = <1>;
};
scmi_pmu: protocol@86 {
reg = <0x86>;
#clock-cells = <1>;
};
};
rimps_log: qcom,rimps_log@17d09c00 {
compatible = "qcom,rimps-log";
reg = <0x17d09c00 0x200>, <0x17d09e00 0x200>;
mboxes = <&rimps 1>;
};
ipcc_mproc: qcom,ipcc@ed18000 {
compatible = "qcom,ipcc";
reg = <0x408000 0x1000>;