mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
Merge "ARM: dts: msm: Add QUPv3_0 and SE5 dt nodes for SHIMA"
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@@ -8,6 +8,34 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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qupv3_se13_2uart_pins: qupv3_se13_2uart_pins {
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qupv3_se13_2uart_active: qupv3_se13_2uart_active {
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mux {
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pins = "gpio18", "gpio19";
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function = "qup13";
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};
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config {
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pins = "gpio18", "gpio19";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se13_2uart_sleep: qupv3_se13_2uart_sleep {
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mux {
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pins = "gpio18", "gpio19";
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function = "gpio";
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};
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config {
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pins = "gpio18", "gpio19";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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};
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};
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33
qcom/shima-qupv3.dtsi
Normal file
33
qcom/shima-qupv3.dtsi
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@@ -0,0 +1,33 @@
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#include <dt-bindings/interconnect/qcom,shima.h>
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&soc {
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x9c0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
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<MASTER_QUP_0 SLAVE_EBI1>;
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iommus = <&apps_smmu 0x4c3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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};
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/* Debug UART Instance */
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qupv3_se13_2uart: qcom,qup_uart@994000 {
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compatible = "qcom,msm-geni-console";
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reg = <0x994000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se13_2uart_active>;
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pinctrl-1 = <&qupv3_se13_2uart_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "ok";
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};
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};
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@@ -1131,6 +1131,7 @@
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#include "shima-pinctrl.dtsi"
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#include "shima-pm.dtsi"
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#include "shima-stub-regulator.dtsi"
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#include "shima-qupv3.dtsi"
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#include "shima-gdsc.dtsi"
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#include "shima-ion.dtsi"
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#include "shima-usb.dtsi"
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