Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: Update GPUCC node and its gdsc's for RAVELIN

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Update graphics clock controller node and its corresponding gdsc's
for RAVELIN platform.

Change-Id: I6973e5888eb9b654f75e879d6c50fa3b57d266e5
This commit is contained in:
Kalpak Kawadkar
2022-07-13 16:46:08 +05:30
parent aa99cdcadb
commit bd91dc5af1
2 changed files with 24 additions and 4 deletions
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7
qcom/ravelin-rumi.dtsi
View File

@@ -187,3 +187,10 @@
clocks = <&bi_tcxo>, <&bi_tcxo_ao>,
<&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
};
&gpucc {
clocks = <&bi_tcxo>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
};

21
qcom/ravelin.dtsi
View File

@@ -746,8 +746,17 @@
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,dummycc";
clock-output-names = "gpucc_clocks";
compatible = "qcom,ravelin-gpucc", "syscon";
reg = <0x3d90000 0xa000>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
clock-names = "bi_tcxo", "gpll0_out_main",
"gpll0_out_main_div", "gcc_gpu_snoc_dvm_gfx_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -1442,12 +1451,16 @@
};
&gpu_cc_cx_gdsc {
compatible = "regulator-fixed";
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gpu_cc_gx_gdsc {
compatible = "regulator-fixed";
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
sw-reset = <&gpu_cc_gx_sw_reset>;
status = "ok";
};