Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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Merge "bindings: clock: Add support for SHIMA clock controllers"

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qctecmdr
2020-04-15 04:56:57 -07:00
committed by Gerrit - the friendly Code Review server
parent 20416ff138 4600b9ccf5
commit d1069f73af
6 changed files with 8 additions and 3 deletions
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3
bindings/clock/qcom,camcc.txt
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@@ -2,7 +2,8 @@ Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding
-------------------------------------------------------------------
Required properties :
- compatible : shall contain "qcom,sdm845-camcc" or "qcom,lahaina-camcc".
- compatible : shall contain "qcom,sdm845-camcc" or "qcom,lahaina-camcc",
"qcom,shima-camcc".
- reg : shall contain base register location and length.
- reg-names: names of registers listed in the same order as in
the reg property.

2
bindings/clock/qcom,debugcc.txt
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@@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. Debug Clock Controller Binding
----------------------------------------------------------
Required properties :
- compatible: Shall contain "qcom,lahaina-debugcc".
- compatible: Shall contain "qcom,lahaina-debugcc" or "qcom,shima-debugcc".
- qcom,gcc: phandle to the GCC device node.
- qcom,videocc: phandle to the Video CC device node.
- qcom,camcc: phandle to the Camera CC device node.

1
bindings/clock/qcom,dispcc.txt
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@@ -7,6 +7,7 @@ Required properties :
"qcom,sdm845-dispcc"
"qcom,lahaina-dispcc"
"qcom,shima-dispcc"
- reg : shall contain base register location and length.
- #clock-cells : from common clock binding, shall contain 1.

1
bindings/clock/qcom,gcc.txt
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@@ -28,6 +28,7 @@ Required properties :
"qcom,gcc-sm8150-v2"
"qcom,gcc-sa8155"
"qcom,gcc-sa8155-v2"
"qcom,shima-gcc"
- reg : shall contain base register location and length

3
bindings/clock/qcom,gpucc.txt
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@@ -3,7 +3,8 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
Required properties :
- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc",
"qcom,lahaina-gpucc.
"qcom,lahaina-gpucc",
"qcom,shima-gpucc".
- reg: shall contain base register offset and size.
- reg-names: names of registers listed in the same order as in the reg property.
Must contain "cc_base".

1
bindings/clock/qcom,videocc.txt
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@@ -6,6 +6,7 @@ Required properties :
"qcom,sdm845-videocc"
"qcom,lahaina-videocc"
"qcom,shima-videocc"
- reg : shall contain base register location and length
- #clock-cells : from common clock binding, shall contain 1.