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ARM: dts: msm: add dma-coherent option for etr1

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Add dma-coherent option for etr1 on diwali and waipio to fix
dma_sync_for_single_cpu() issue, which cause by a upstream
change "Speed up for bounce buffer in flat mode". this change
uses “dma_alloc_noncoherent + cache sync” to replace
dma_alloc_coherent, These APIs only work with contiguous memory.
since etr support iommu, etr buffer physical address is not
contiguous.

Change-Id: Ib179a65c49e893cc3a77d7accfeb6515e0d02e23
This commit is contained in:
Yuanfang Zhang
2022-02-23 16:24:23 +08:00
parent 6d6f415a81
commit e001a217d0
2 changed files with 2 additions and 0 deletions
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1
qcom/diwali-coresight.dtsi
View File

@@ -3088,6 +3088,7 @@
iommus = <&apps_smmu 0x0500 0>;
qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
dma-coherent;
coresight-csr = <&csr>;
csr-atid-offset = <0x104>;

1
qcom/waipio-coresight.dtsi
View File

@@ -3336,6 +3336,7 @@
iommus = <&apps_smmu 0x0620 0>;
qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
dma-coherent;
coresight-csr = <&csr>;
csr-atid-offset = <0x104>;