Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees synced 2026-02-01 08:51:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

ARM: dts: msm: add pull-up for spi cs pin

Browse Source 
If crash happens on Helios side, helios reconfigure the spi, it
will read the spi_cfg enable bit in polling mode till the enable
bit is set. This enable bit is set only if the CS is high. Master
driver keeps all pins in sleep state including CS once transfer is
completed. Due to this Helios side slave gest stuck in the while
loop awaiting enable bit to get set. To solve this, add bias-pull-up
for CS line during sleep state of Master driver.

Change-Id: I8e54e227c0dc411d898a57b8b282ebf24a931900
This commit is contained in:
Anil Veshala Veshala
2022-04-26 05:35:18 -07:00
parent 0fe020ae2b
commit edee07f300
2 changed files with 33 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
qcom/neo-pinctrl.dtsi
View File

@@ -866,13 +866,13 @@
qupv3_se3_spi_active: qupv3_se3_spi_active {
mux {
pins = "gpio16", "gpio17",
"gpio18", "gpio19";
"gpio18";
function = "qup0_se3";
};
config {
pins = "gpio16", "gpio17",
"gpio18", "gpio19";
"gpio18";
drive-strength = <6>;
bias-disable;
};
@@ -881,17 +881,44 @@
qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
mux {
pins = "gpio16", "gpio17",
"gpio18", "gpio19";
"gpio18";
function = "gpio";
};
config {
pins = "gpio16", "gpio17",
"gpio18", "gpio19";
"gpio18";
drive-strength = <6>;
bias-disable;
};
};
qupv3_se3_spi_cs0_active: qupv3_se3_spi_cs0_active {
mux {
pins = "gpio19";
function = "qup0_se3";
};
config {
pins = "gpio19";
drive-strength = <6>;
bias-pull-up;
};
};
qupv3_se3_spi_cs0_sleep: qupv3_se3_spi_cs0_sleep {
mux {
pins = "gpio19";
function = "gpio";
};
config {
pins = "gpio19";
drive-strength = <6>;
/* Helios specific CS requirement. */
bias-pull-up;
};
};
};
qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {

4
qcom/neo-qupv3.dtsi
View File

@@ -220,8 +220,8 @@
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_spi_active>;
pinctrl-1 = <&qupv3_se3_spi_sleep>;
pinctrl-0 = <&qupv3_se3_spi_active>, <&qupv3_se3_spi_cs0_active>;
pinctrl-1 = <&qupv3_se3_spi_sleep>, <&qupv3_se3_spi_cs0_sleep>;
dmas = <&gpi_dma0 0 3 1 64 0>,
<&gpi_dma0 1 3 1 64 0>;
dma-names = "tx", "rx";