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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ARM: dts: msm: Enabled IPCC_Compute_L0 & IPCLite protocol
These changes enable IPCLite communication protocol and IPCC_Compute_L0 interrupt of IPCC HW controller. IPCLite protocol relies on IPCC Compute_l0 interrupt for its inter-proc signalling. Change-Id: Ic4865e6e0e216f1f0aa75fe44bb89904cc989fd5
This commit is contained in:
smaniar
79
bindings/soc/qcom/qcom,ipclite.txt
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79
bindings/soc/qcom/qcom,ipclite.txt
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@@ -0,0 +1,79 @@
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Qualcomm Technologies, Inc. IPCLite Framework
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This binding describes IPCLite protocol within the system.
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IPCLite is a light weight mechanism for communication between
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subsystem-pairs. This protocol will be primarily used to
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support low-latency signalling for Global Synx framework.
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- compatible :
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Usage: required
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Value type: <stringlist>
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Definition: must be "qcom,ipclite"
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- label:
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Usage: optional
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Value type: <string>
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Definition: should specify the subsystem name this edge corresponds to.
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the IRQ used by the remote processor to
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signal this processor about communication related events
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- qcom,remote-pid:
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Usage: required for ipcmem
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Value type: <u32>
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Definition: specifies the identifier of the remote endpoint of this edge
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- mboxes:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the "rpm_hlos" mailbox in APCS, as described
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in mailbox/mailbox.txt
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= EXAMPLE
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The following example represents the IPCLite node along with cdsp sub-node.
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ipclite {
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compatible = "qcom,ipclite";
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memory-region = <&global_sync_mem>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ipclite_cdsp: cdsp {
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qcom,remote-pid = <5>;
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label = "cdsp";
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ipclite_signal_0 {
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index = <0>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_1 {
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index = <1>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_2 {
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index = <2>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
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IRQ_TYPE_EDGE_RISING>;
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};
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};
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};
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198
qcom/waipio.dtsi
198
qcom/waipio.dtsi
@@ -1559,6 +1559,204 @@
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#mbox-cells = <2>;
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};
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ipcc_compute_l0: qcom,ipcc_compute_l0@408000 {
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compatible = "qcom,ipcc";
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reg = <0x408000 0x1000>;
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interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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ipclite {
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compatible = "qcom,ipclite";
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memory-region = <&global_sync_mem>;
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hwlocks = <&tcsr_mutex 11>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ipclite_apss: apss {
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qcom,remote-pid = <0>;
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label = "apss";
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ipclite_signal_0 {
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index = <0>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_APSS
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_1 {
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index = <1>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_BROADCAST
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_BROADCAST
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_2 {
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index = <2>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_APSS
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_3 {
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index = <3>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_APSS
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
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IRQ_TYPE_EDGE_RISING>;
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};
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};
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ipclite_cdsp: cdsp {
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qcom,remote-pid = <5>;
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label = "cdsp";
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ipclite_signal_0 {
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index = <0>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_1 {
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index = <1>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_2 {
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index = <2>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_3 {
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index = <3>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CDSP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
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IRQ_TYPE_EDGE_RISING>;
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};
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};
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ipclite_cvp: cvp {
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qcom,remote-pid = <6>;
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label = "cvp";
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ipclite_signal_0 {
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index = <0>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CVP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_1 {
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index = <1>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CVP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_2 {
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index = <2>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CVP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_3 {
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index = <3>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_CVP
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
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IRQ_TYPE_EDGE_RISING>;
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};
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};
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ipclite_vpu: vpu {
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qcom,remote-pid = <8>;
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label = "vpu";
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ipclite_signal_0 {
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index = <0>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_VPU
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_1 {
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index = <1>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_VPU
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_2 {
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index = <2>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_VPU
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
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IRQ_TYPE_EDGE_RISING>;
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};
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ipclite_signal_3 {
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index = <3>;
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mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
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interrupt-parent = <&ipcc_compute_l0>;
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interrupts = <IPCC_CLIENT_VPU
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IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
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IRQ_TYPE_EDGE_RISING>;
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};
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};
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};
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tcsr: syscon@1fc0000 {
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compatible = "syscon";
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reg = <0x1fc0000 0x30000>;
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