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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: Add support for Ravelin GPU
Add the necessary DT nodes to support GPU in Ravelin. Change-Id: I5e19f54dcb4a193250dc26bb3e4792f15432d235
This commit is contained in:
Harshitha Sai Neelati
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Gerrit - the friendly Code Review server
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b9746e2ef2
commit
fc3ec1c07c
277
qcom/ravelin-gpu.dtsi
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277
qcom/ravelin-gpu.dtsi
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@@ -0,0 +1,277 @@
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#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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&soc {
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msm_gpu: qcom,kgsl-3d0@3d00000 {
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compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-gen6-3-26-0";
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status = "ok";
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reg = <0x3d00000 0x40000>, <0x03d61000 0x800>,
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<0x03d7d000 0x1D000>, <0x03d9e000 0x1000>,
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<0x10900000 0x80000>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "gmu_wrapper",
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"cx_misc", "qdss_gfx";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&aoss_qmp>,
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<&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>;
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clock-names = "core_clk",
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"gmu_clk",
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"mem_clk",
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"mem_iface_clk",
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"hub_cx_int_clk",
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"smmu_vote",
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"apb_pclk",
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"gpu_cc_cx_gmu",
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"gpu_cc_hub_cx_int",
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"gpu_cc_hlos1_vote_gpu_smmu",
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"gcc_gpu_memnoc_gfx",
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"gcc_gpu_snoc_dvm_gfx",
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"gpu_cc_ahb";
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regulator-names = "vddcx", "vdd";
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vddcx-supply = <&gpu_cc_cx_gdsc>;
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vdd-supply = <&gpu_cc_gx_gdsc>;
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qcom,chipid = <0x06010300>;
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qcom,gpu-model = "Adreno613v1";
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qcom,no-nap;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <2>;
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qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
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qcom,tzone-names = "gpuss";
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-ddr7 =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* index=1 LOW_SVS */
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<MHZ_TO_KBPS(547, 4)>, /* index=2 LOW_SVS */
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<MHZ_TO_KBPS(768, 4)>, /* index=3 SVS */
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<MHZ_TO_KBPS(1017, 4)>, /* index=4 SVS */
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<MHZ_TO_KBPS(1353, 4)>, /* index=5 SVS_L1 */
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<MHZ_TO_KBPS(1555, 4)>, /* index=6 NOM */
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<MHZ_TO_KBPS(1708, 4)>, /* index=7 NOM */
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<MHZ_TO_KBPS(2133, 4)>; /* index=8 TURBO */
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qcom,bus-table-ddr8 =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(200, 4)>, /* index=1 LOW_SVS */
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<MHZ_TO_KBPS(451, 4)>, /* index=2 LOW_SVS */
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<MHZ_TO_KBPS(547, 4)>, /* index=3 LOW_SVS */
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<MHZ_TO_KBPS(681, 4)>, /* index=4 SVS */
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<MHZ_TO_KBPS(768, 4)>, /* index=5 SVS */
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<MHZ_TO_KBPS(1555, 4)>, /* index=6 SVS */
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<MHZ_TO_KBPS(1708, 4)>, /* index=7 SVS_L1 */
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<MHZ_TO_KBPS(2092, 4)>, /* index=8 NOM */
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<MHZ_TO_KBPS(2736, 4)>, /* index=9 TURBO */
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<MHZ_TO_KBPS(3196, 4)>; /* index=10 TURBO */
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/* Enable context aware freq. scaling */
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qcom,enable-ca-jump;
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/* Context aware jump busy penalty in us */
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qcom,ca-busy-penalty = <12000>;
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zap-shader {
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memory-region = <&gpu_microcode_mem>;
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};
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-reserved = <2048>;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-reserved = <1024>;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 128K Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <131072>;
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qcom,mempool-reserved = <128>;
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};
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/* 256K Page Pool configuration */
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qcom,gpu-mempool@4 {
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reg = <4>;
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qcom,mempool-page-size = <262144>;
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qcom,mempool-reserved = <80>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@5 {
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reg = <5>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,initial-pwrlevel = <6>;
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qcom,ca-target-pwrlevel = <5>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <1010000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <10>;
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qcom,bus-min-ddr8 = <10>;
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qcom,bus-max-ddr8 = <10>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <955000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <9>;
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qcom,bus-min-ddr8 = <9>;
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qcom,bus-max-ddr8 = <10>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <850000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <9>;
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qcom,bus-min-ddr8 = <8>;
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qcom,bus-max-ddr8 = <10>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <765000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <7>;
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qcom,bus-min-ddr7 = <6>;
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qcom,bus-max-ddr7 = <8>;
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qcom,bus-freq-ddr8 = <8>;
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qcom,bus-min-ddr8 = <7>;
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qcom,bus-max-ddr8 = <9>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <605000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <7>;
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qcom,bus-freq-ddr8 = <7>;
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qcom,bus-min-ddr8 = <6>;
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qcom,bus-max-ddr8 = <8>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <500000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <5>;
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qcom,bus-freq-ddr8 = <6>;
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qcom,bus-min-ddr8 = <5>;
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qcom,bus-max-ddr8 = <7>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <340000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <4>;
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qcom,bus-freq-ddr8 = <3>;
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qcom,bus-min-ddr8 = <3>;
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qcom,bus-max-ddr8 = <6>;
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};
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x03da0000 0x40000>;
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vddcx-supply = <&gpu_cc_cx_gdsc>;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x0 0x400>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x2 0x400>;
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qcom,iommu-dma = "disabled";
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};
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};
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};
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@@ -327,6 +327,7 @@
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};
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#include "msm-arm-smmu-ravelin.dtsi"
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#include "ravelin-gpu.dtsi"
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#include "ravelin-dma-heaps.dtsi"
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#include "ravelin-reserved-memory.dtsi"
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#include "ravelin-dma-heaps.dtsi"
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