Update device tree node for gpu cc and enable peripheral
gpu graphics controller clock driver on Lahaina.
Change-Id: Ie5d459fdf4fd7bbde3d514823788c7ad9b1aa5be
Add global distributed switch controller (GDSC) device nodes for
the GDSCs managed by the application processor on Lahaina.
Change-Id: I63d013808d7752dca38e941cd6db7eb85cc01d9c
Replace the stub-regulator device nodes for the PMIC PM8350,
PM8350C, and PMR735A regulators with rpmh-regulator device nodes.
This ensures that consumers are able to modify the physical state
of these PMIC regulators.
Keep VDD_CX, VDD_MXA, VDD_MXC, and VDD_MMCX always-on at Turbo
voltage level to avoid initialization issues before proxy voting
is available.
Leave the stub-regulator device for PM8350 LDO 7 in place as
RPMh does not yet support 2.7 V required by UFS.
Change-Id: Ie6357fb98d5568a9d601df93017f1220103d1ace
Add bcm voter devices that live under RSC devices
to allow interconnect providers to target their
votes for meeting bandwidth constraints.
Change-Id: I83f320bff8a37cf6d101d225061961c900d7140e
Update the minimum and maximum voltage limits for PMIC regulators
on Lahaina boards to match the latest hardware guidelines.
Change-Id: I6ec65dbb5a4d6fd5829e4ce3b39cc351d78abbf8
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn used by EAS to take
placement decisions.
Change-Id: Ia44ffe4fcb799663c4bb47eb18f1ac79952ed12d
Add device node for the smp2p sleepstate entry and the device node for
the smp2p sleep driver to notify dsps of apps power state changes.
Change-Id: I9f413636e98d620bfab4729afc20d9783e3a24a5
Add the QMP and QMP DEBUGFS node to facilitiate communication with AOP.
The QMP driver sends messages using the AOP msgram with a mailbox like
protocol.
Change-Id: Id67ef57b2895f98a486d5ee2724205f1d6b5e41e
Add qcom,msm-hang-detect to device tree to enable MSM Core Hang
Detection on all cores.
Changed from 2 nodes (one for each of silver and gold) to 1 node because
that's semantically correct for the driver.
Change-Id: I10be3a765e20460f43ce4a8cb5e6580d99439f46
The ION carveout heap manages the carveouts under its domain
by relying on the assumption that the kernel is aware of this
memory. When the memory is marked as "no-map", the kernel
does not maintain any information about the memory, which
prevents the carveout heap from managing the memory. Thus,
allow for the carveout heap memory to be mapped by the kernel.
Change-Id: I6516d2cd8fcacdb975a3190254e79bbce51e1d24
Add lahaina-usb.dtsi which defines USB controller nodes and no-op
PHY. In addition, add entries for the emulation PHY to
lahaina-rumi.dtsi with overrides to limit the USB instances to
high-speed, peripheral-only.
Change-Id: I987a18c07c5406de3c924fcf03db13a72e9ab2de
To prevent the possibility of running out of stream-matching
entries (SMEs) on the KGSL SMMU in cases where all the SMEs
are required, disable the coherent KGSL IOMMU test device.
Change-Id: I1d1cf1a4530680de91c839d22f057b807765111d
Update the board-id property to include major and minor ids as well
for the bootloader to pick the correct version of devicetree.
Change-Id: I9403d2b2fb88e55db4e68ceea9d884d507167cc7
The PIL drivers need to vote for bandwidth across DDR and
crypto subsytem, such that the secure world can perform
initialization and authorization of the firmware blobs.
Hence add a device-tree node indicating the corresponding
interconnect.
Change-Id: If5626ad20638434e39a7d4aa0f02149a72bdaf12
Add edac node with compatibility of arm,arm64-kryo-cpu-erp,
to enable error reporting capability for L1/L2 & L3 memories
on Lahaina SoC.
Change-Id: Id561334e40c0aaf04348db90df4a30252ded2432
Fix the size of the register space for the graphics SMMU,
and enable it, as well as the associated test devices.
Change-Id: I5963b9d5a5fb0ad1d55a1e2011ee1bfb5d961fee
