Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Set QSERDES_COM_SYSCLK_EN to 0x8 for PCIe2 PHY for sdxpinn"

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qctecmdr
2022-11-24 13:42:34 -08:00
committed by Gerrit - the friendly Code Review server
parent 87cea4eada 680058afe8
commit 24ee62d73f
1 changed files with 4 additions and 4 deletions
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8
qcom/sdxpinn-pcie.dtsi
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@@ -105,8 +105,8 @@
<0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_BCR>,
<&gcc GCC_PCIE_PHY_BCR>;
reset-names = "pcie_core_reset",
"pcie_phy_reset";
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
qcom,smmu-sid-base = <0x0800>;
iommu-map = <0x0 &apps_smmu 0x0800 0x1>,
@@ -650,7 +650,7 @@
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
<&gcc GCC_PCIE_2_CLKREF_EN>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_2_PIPE_DIV2_CLK>,
<&gcc GCC_PCIE_2_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_2_PIPE_CLK_SRC>,
@@ -721,7 +721,7 @@
0x00e0 0x90 0x0
0x00e4 0x82 0x0
0x00f4 0x07 0x0
0x0110 0x04 0x0
0x0110 0x08 0x0
0x0120 0x42 0x0
0x0140 0x14 0x0
0x0164 0x34 0x0