Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add initial device tree for MHI on cinder"

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qctecmdr
2022-02-09 10:52:08 -08:00
committed by Gerrit - the friendly Code Review server
parent b2acbf2b17 a40c8ce42b
commit 2ffcf98f2e
3 changed files with 151 additions and 0 deletions
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41
qcom/cinder-pinctrl.dtsi
View File

@@ -76,4 +76,45 @@
bias-pull-down;
};
};
pcie_ep {
pcie_ep_clkreq_default: pcie_ep_clkreq_default {
mux {
pins = "gpio99";
function = "pcie_clkreq";
};
config {
pins = "gpio99";
drive-strength = <2>;
bias-disable;
};
};
pcie_ep_perst_default: pcie_ep_perst_default {
mux {
pins = "gpio98";
function = "gpio";
};
config {
pins = "gpio98";
drive-strength = <2>;
bias-pull-down;
};
};
pcie_ep_wake_default: pcie_ep_wake_default {
mux {
pins = "gpio100";
function = "gpio";
};
config {
pins = "gpio100";
drive-strength = <2>;
bias-disable;
};
};
};
};

16
qcom/cinder-rumi.dtsi
View File

@@ -11,6 +11,22 @@
};
&soc {
pcie_ep: qcom,pcie@48020000 {
compatible = "qcom,pcie-ep";
reg = <0x48020000 0x10000>,
<0x48000000 0xf20>,
<0x48000f40 0xa8>,
<0x48010000 0x10000>,
<0x01c00000 0x4000>,
<0x01c10000 0x10000>,
<0x01c04000 0x1000>,
<0x01c09054 0x4>;
reg-names = "msi", "dm_core", "elbi", "iatu",
"parf", "phy", "mmio", "rumi";
qcom,pcie-link-speed = <1>;
qcom,tcsr-not-supported;
};
};

94
qcom/cinder.dtsi
View File

@@ -501,6 +501,100 @@
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
};
pcie_ep: qcom,pcie@48020000 {
compatible = "qcom,pcie-ep";
reg = <0x48020000 0x10000>,
<0x48000000 0xf20>,
<0x48000f40 0xa8>,
<0x48010000 0x10000>,
<0x48002000 0x1400>,
<0x48004000 0x1000>,
<0x01c00000 0x4000>,
<0x01c10000 0x10000>,
<0x01c04000 0x1000>,
<0x01fcb000 0x1000>,
<0xc2f1000 0x4>;
reg-names = "msi", "dm_core", "elbi", "iatu",
"msix_table", "msix_pba", "parf",
"phy", "mmio", "tcsr_pcie_perst_en",
"aoss_cc_reset";
#address-cells = <0>;
interrupt-parent = <&pcie_ep>;
interrupts = <0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 172 0>;
interrupt-names = "int_global";
pinctrl-names = "default";
pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
&pcie_ep_wake_default>;
clkreq-gpio = <&tlmm 99 0>;
perst-gpio = <&tlmm 98 0>;
wake-gpio = <&tlmm 100 0>;
gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
vreg-1p8-supply = <&pm8150_a_l3>;
vreg-0p9-supply = <&pm8150_a_l6>;
vreg-mx-supply = <&VDD_MX_LEVEL>;
qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>;
qcom,vreg-0p9-voltage-level = <912000 912000 132000>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX RPMH_REGULATOR_LEVEL_NOM 0>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk",
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
"pcie_aux_clk", "pcie_ldo",
"pcie_slv_q2a_axi_clk",
"pcie_0_ref_clk_src";
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "pcie_core_reset",
"pcie_phy_reset";
qcom,pcie-vendor-id = /bits/ 16 <0x17cb>;
qcom,pcie-device-id = /bits/ 16 <0x0600>;
qcom,pcie-link-speed = <4>;
qcom,pcie-phy-ver = <6>;
qcom,pcie-active-config;
qcom,pcie-aggregated-irq;
qcom,pcie-mhi-a7-irq;
qcom,phy-status-reg2 = <0x1214>;
qcom,mhi-soc-reset-offset = <0xb01b8>;
qcom,aux-clk = <0x11>;
status = "ok";
};
mhi_device: mhi_dev@1c04000 {
compatible = "qcom,msm-mhi-dev";
reg = <0x1c04000 0x1000>;
reg-names = "mhi_mmio_base";
qcom,mhi-ep-msi = <0>;
qcom,mhi-version = <0x1000000>;
qcom,use-mhi-dma-software-channel;
interrupts = <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mhi-device-inta";
qcom,mhi-ifc-id = <0x060017cb>;
qcom,mhi-interrupt;
qcom,no-m0-timeout;
status = "ok";
};
mhi_net_device: qcom,mhi_net_dev {
compatible = "qcom,msm-mhi-dev-net";
status = "ok";
};
};
&firmware {