mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 05:00:27 +00:00
Add 'qcom/video/' from commit '9ad63df640420efc37b5f53f6d616b0421f8913d'
git-subtree-dir: qcom/video git-subtree-mainline:2acdfb55cbgit-subtree-split:9ad63df640
This commit is contained in:
Bruno Martins
17
qcom/video/Kbuild
Normal file
17
qcom/video/Kbuild
Normal file
@@ -0,0 +1,17 @@
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ifeq ($(CONFIG_ARCH_WAIPIO), y)
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dtbo-y += waipio-vidc.dtbo
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endif
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ifeq ($(CONFIG_ARCH_KALAMA), y)
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dtbo-y += kalama-vidc.dtbo
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dtbo-y += kalama-vidc-v2.dtbo
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endif
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ifeq ($(CONFIG_ARCH_ANORAK), y)
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dtbo-y += anorak-vidc.dtbo
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endif
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always-y := $(dtb-y) $(dtbo-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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9
qcom/video/Makefile
Normal file
9
qcom/video/Makefile
Normal file
@@ -0,0 +1,9 @@
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KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
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all: dtbs
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
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%:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
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16
qcom/video/anorak-vidc.dts
Normal file
16
qcom/video/anorak-vidc.dts
Normal file
@@ -0,0 +1,16 @@
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-anorak.h>
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#include <dt-bindings/interconnect/qcom,anorak.h>
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#include <dt-bindings/clock/qcom,videocc-anorak.h>
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#include "anorak-vidc.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Anorak";
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compatible = "qcom,anorak";
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qcom,msm-id = <549 0x10000>;
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qcom,board-id = <0 0>, <0x10021 0x0>, <0x10022 0x0>, <0x10026 0x0>,
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<0x10022 0x1>, <0x10022 0x2>, <0x10022 0x3>;
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};
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110
qcom/video/anorak-vidc.dtsi
Normal file
110
qcom/video/anorak-vidc.dtsi
Normal file
@@ -0,0 +1,110 @@
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&soc {
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msm_vidc: qcom,vidc@aa00000 {
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compatible = "qcom,msm-vidc", "qcom,msm-vidc-anorak", "qcom,msm-vidc-iris3";
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status = "okay";
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reg = <0x0aa00000 0xF0000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&video_mem>;
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pas-id = <9>;
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/* IOMMU Config */
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#address-cells = <1>;
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#size-cells = <1>;
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/* LLCC Cache */
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cache-slice-names = "vidsc0";
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/* Supply */
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iris-ctl-supply = <&video_cc_mvs0c_gdsc>;
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vcodec-supply = <&video_cc_mvs0_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"core_clk", "vcodec_clk", "video_cc_mvs0_clk_src";
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clock-ids = <GCC_VIDEO_AXI0_CLK VIDEO_CC_MVS0C_CLK
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VIDEO_CC_MVS0_CLK VIDEO_CC_MVS0_CLK_SRC>;
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clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
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<&videocc VIDEO_CC_MVS0C_CLK>,
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<&videocc VIDEO_CC_MVS0_CLK>,
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<&videocc VIDEO_CC_MVS0_CLK_SRC>;
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qcom,proxy-clock-names = "gcc_video_axi0",
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"core_clk", "vcodec_clk", "video_cc_mvs0_clk_src";
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/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
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qcom,clock-configs = <0x0 0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <240000000 338000000
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366000000 444000000 533000000>;
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qcom,reg-presets = <0xB0088 0x0 0x11>;
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/* Video Firmware ELF image name */
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vidc,firmware-name = "vpu33_4v";
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/* Bus Interconnects */
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interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc";
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interconnects = <&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_VENUS_CFG>,
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<&mc_virt MASTER_LLCC
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&mc_virt SLAVE_EBI1>,
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<&mmss_noc MASTER_VIDEO
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&gem_noc SLAVE_LLCC>;
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/* Bus BW range (low, high) for each bus */
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qcom,bus-range-kbps = <1000 1000
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1000 15000000
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1000 15000000>;
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/* MMUs */
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non_secure_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_ns_pixel";
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iommus = <&apps_smmu 0x0987 0x0400>;
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qcom,iommu-dma-addr-pool = <0x00100000 0xdff00000>;
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qcom,iommu-faults = "non-fatal";
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virtual-addr-pool = <0x00100000 0xdff00000>;
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dma-coherent;
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};
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non_secure_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_ns";
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iommus = <&apps_smmu 0x0980 0x0400>;
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qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
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qcom,iommu-faults = "non-fatal";
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virtual-addr-pool = <0x25800000 0xba800000>;
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dma-coherent;
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};
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secure_non_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_non_pixel";
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iommus = <&apps_smmu 0x0984 0x0400>;
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qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */
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virtual-addr-pool = <0x01000000 0x24800000>;
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qcom,secure-context-bank;
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};
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secure_bitstream_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_bitstream";
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iommus = <&apps_smmu 0x0981 0x0404>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
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virtual-addr-pool = <0x00500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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secure_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_pixel";
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iommus = <&apps_smmu 0x0983 0x0400>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
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virtual-addr-pool = <0x00500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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};
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};
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15
qcom/video/kalama-vidc-v2.dts
Normal file
15
qcom/video/kalama-vidc-v2.dts
Normal file
@@ -0,0 +1,15 @@
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-kalama.h>
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#include <dt-bindings/interconnect/qcom,kalama.h>
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#include <dt-bindings/clock/qcom,videocc-kalama.h>
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#include "kalama-vidc-v2.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Kalama";
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compatible = "qcom,kalama";
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qcom,msm-id = <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>;
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qcom,board-id = <0 0>;
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};
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9
qcom/video/kalama-vidc-v2.dtsi
Normal file
9
qcom/video/kalama-vidc-v2.dtsi
Normal file
@@ -0,0 +1,9 @@
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#include "kalama-vidc.dtsi"
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/* KalamaV2-specific changes */
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&msm_vidc {
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qcom,allowed-clock-rates = <240000000 338000000
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366000000 444000000 533333333>;
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};
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15
qcom/video/kalama-vidc.dts
Normal file
15
qcom/video/kalama-vidc.dts
Normal file
@@ -0,0 +1,15 @@
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-kalama.h>
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#include <dt-bindings/interconnect/qcom,kalama.h>
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#include <dt-bindings/clock/qcom,videocc-kalama.h>
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#include "kalama-vidc.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Kalama";
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compatible = "qcom,kalama";
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qcom,msm-id = <519 0x10000>, <536 0x10000>, <600 0x10000>, <601 0x10000>;
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qcom,board-id = <0 0>;
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};
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112
qcom/video/kalama-vidc.dtsi
Normal file
112
qcom/video/kalama-vidc.dtsi
Normal file
@@ -0,0 +1,112 @@
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&soc {
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msm_vidc: qcom,vidc@aa00000 {
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compatible = "qcom,msm-vidc", "qcom,msm-vidc-kalama", "qcom,msm-vidc-iris3";
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status = "okay";
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reg = <0x0aa00000 0xF0000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&video_mem>;
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pas-id = <9>;
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/* IOMMU Config */
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#address-cells = <1>;
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#size-cells = <1>;
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/* LLCC Cache */
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cache-slice-names = "vidsc0", "vidvsp";
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/* Supply */
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iris-ctl-supply = <&video_cc_mvs0c_gdsc>;
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vcodec-supply = <&video_cc_mvs0_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"core_clk", "vcodec_clk", "video_cc_mvs0_clk_src";
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clock-ids = <GCC_VIDEO_AXI0_CLK VIDEO_CC_MVS0C_CLK
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VIDEO_CC_MVS0_CLK VIDEO_CC_MVS0_CLK_SRC>;
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clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
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<&videocc VIDEO_CC_MVS0C_CLK>,
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<&videocc VIDEO_CC_MVS0_CLK>,
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<&videocc VIDEO_CC_MVS0_CLK_SRC>;
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qcom,proxy-clock-names = "gcc_video_axi0",
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"core_clk", "vcodec_clk", "video_cc_mvs0_clk_src";
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/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
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qcom,clock-configs = <0x0 0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <240000000 338000000
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366000000 444000000 481000000>;
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resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
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reset-names = "video_axi_reset";
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qcom,reg-presets = <0xB0088 0x0 0x11>;
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/* Video Firmware ELF image name */
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vidc,firmware-name = "vpu30_4v";
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|
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/* Bus Interconnects */
|
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interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc";
|
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interconnects = <&gem_noc MASTER_APPSS_PROC
|
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&config_noc SLAVE_VENUS_CFG>,
|
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<&mc_virt MASTER_LLCC
|
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&mc_virt SLAVE_EBI1>,
|
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<&mmss_noc MASTER_VIDEO
|
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&gem_noc SLAVE_LLCC>;
|
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/* Bus BW range (low, high) for each bus */
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qcom,bus-range-kbps = <1000 1000
|
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1000 15000000
|
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1000 15000000>;
|
||||
|
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/* MMUs */
|
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non_secure_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
|
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label = "venus_ns_pixel";
|
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iommus = <&apps_smmu 0x1947 0x0000>;
|
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qcom,iommu-dma-addr-pool = <0x00100000 0xdff00000>;
|
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qcom,iommu-faults = "non-fatal";
|
||||
virtual-addr-pool = <0x00100000 0xdff00000>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
non_secure_cb {
|
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compatible = "qcom,msm-vidc,context-bank";
|
||||
label = "venus_ns";
|
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iommus = <&apps_smmu 0x1940 0x0000>;
|
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qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
virtual-addr-pool = <0x25800000 0xba800000>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
secure_non_pixel_cb {
|
||||
compatible = "qcom,msm-vidc,context-bank";
|
||||
label = "venus_sec_non_pixel";
|
||||
iommus = <&apps_smmu 0x1944 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */
|
||||
virtual-addr-pool = <0x01000000 0x24800000>;
|
||||
qcom,secure-context-bank;
|
||||
};
|
||||
|
||||
secure_bitstream_cb {
|
||||
compatible = "qcom,msm-vidc,context-bank";
|
||||
label = "venus_sec_bitstream";
|
||||
iommus = <&apps_smmu 0x1941 0x0004>;
|
||||
qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
|
||||
virtual-addr-pool = <0x00500000 0xdfb00000>;
|
||||
qcom,secure-context-bank;
|
||||
};
|
||||
|
||||
secure_pixel_cb {
|
||||
compatible = "qcom,msm-vidc,context-bank";
|
||||
label = "venus_sec_pixel";
|
||||
iommus = <&apps_smmu 0x1943 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
||||
virtual-addr-pool = <0x00500000 0xdfb00000>;
|
||||
qcom,secure-context-bank;
|
||||
};
|
||||
};
|
||||
};
|
||||
16
qcom/video/waipio-vidc.dts
Normal file
16
qcom/video/waipio-vidc.dts
Normal file
@@ -0,0 +1,16 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-waipio.h>
|
||||
#include <dt-bindings/interconnect/qcom,waipio.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-waipio.h>
|
||||
#include "waipio-vidc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. waipio v1 SoC";
|
||||
compatible = "qcom,waipio";
|
||||
qcom,msm-id = <457 0x10000>, <482 0x10000>,
|
||||
<457 0x20000>, <482 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
118
qcom/video/waipio-vidc.dtsi
Normal file
118
qcom/video/waipio-vidc.dtsi
Normal file
@@ -0,0 +1,118 @@
|
||||
&soc {
|
||||
msm_vidc: qcom,vidc@aa00000 {
|
||||
compatible = "qcom,msm-vidc", "qcom,msm-vidc-waipio", "qcom,msm-vidc-iris2";
|
||||
status = "okay";
|
||||
reg = <0x0aa00000 0xF0000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
memory-region = <&video_mem>;
|
||||
pas-id = <9>;
|
||||
|
||||
/* IOMMU Config */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* LLCC Cache */
|
||||
cache-slice-names = "vidsc0";
|
||||
|
||||
/* Supply */
|
||||
iris-ctl-supply = <&video_cc_mvs0c_gdsc>;
|
||||
vcodec-supply = <&video_cc_mvs0_gdsc>;
|
||||
|
||||
/* Clocks */
|
||||
clock-names = "gcc_video_axi0",
|
||||
"core_clk", "vcodec_clk", "video_cc_mvs0_clk_src";
|
||||
clock-ids = <GCC_VIDEO_AXI0_CLK VIDEO_CC_MVS0C_CLK
|
||||
VIDEO_CC_MVS0_CLK VIDEO_CC_MVS0_CLK_SRC>;
|
||||
clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
|
||||
<&clock_videocc VIDEO_CC_MVS0C_CLK>,
|
||||
<&clock_videocc VIDEO_CC_MVS0_CLK>,
|
||||
<&clock_videocc VIDEO_CC_MVS0_CLK_SRC>;
|
||||
qcom,proxy-clock-names = "gcc_video_axi0",
|
||||
"core_clk", "vcodec_clk", "video_cc_mvs0_clk_src";
|
||||
/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
|
||||
qcom,clock-configs = <0x0 0x0 0x0 0x1>;
|
||||
qcom,allowed-clock-rates = <239999999 338000000
|
||||
366000000 444000000>;
|
||||
resets = <&clock_gcc GCC_VIDEO_AXI0_CLK_ARES>,
|
||||
<&clock_videocc VIDEO_CC_MVS0C_CLK_ARES>;
|
||||
reset-names = "video_axi_reset", "video_core_reset";
|
||||
|
||||
qcom,reg-presets = <0xB0088 0x0 0x11>;
|
||||
|
||||
/* Video Firmware ELF image name */
|
||||
vidc,firmware-name = "vpu20_4v";
|
||||
|
||||
/* Bus Interconnects */
|
||||
interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc";
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC
|
||||
&config_noc SLAVE_VENUS_CFG>,
|
||||
<&mc_virt MASTER_LLCC
|
||||
&mc_virt SLAVE_EBI1>,
|
||||
<&mmss_noc MASTER_VIDEO_P0
|
||||
&gem_noc SLAVE_LLCC>;
|
||||
/* Bus BW range (low, high) for each bus */
|
||||
qcom,bus-range-kbps = <1000 1000
|
||||
1000 15000000
|
||||
1000 15000000>;
|
||||
|
||||
/* MMUs */
|
||||
non_secure_cb {
|
||||
compatible = "qcom,msm-vidc,context-bank";
|
||||
label = "venus_ns";
|
||||
iommus = <&apps_smmu 0x2180 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
|
||||
qcom,iommu-faults = "non-fatal", "stall-disable";
|
||||
qcom,iommu-pagetable = "LLC";
|
||||
virtual-addr-pool = <0x25800000 0xba800000>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
non_secure_pixel_cb {
|
||||
compatible = "qcom,msm-vidc,context-bank";
|
||||
label = "venus_ns_pixel";
|
||||
iommus = <&apps_smmu 0x2187 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x00100000 0xdff00000>;
|
||||
qcom,iommu-faults = "non-fatal", "stall-disable";
|
||||
qcom,iommu-pagetable = "LLC";
|
||||
virtual-addr-pool = <0x00100000 0xdff00000>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
secure_non_pixel_cb {
|
||||
compatible = "qcom,msm-vidc,context-bank";
|
||||
label = "venus_sec_non_pixel";
|
||||
iommus = <&apps_smmu 0x2184 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
|
||||
qcom,iommu-faults = "non-fatal", "stall-disable";
|
||||
qcom,iommu-pagetable = "LLC";
|
||||
qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */
|
||||
virtual-addr-pool = <0x01000000 0x24800000>;
|
||||
qcom,secure-context-bank;
|
||||
};
|
||||
|
||||
secure_bitstream_cb {
|
||||
compatible = "qcom,msm-vidc,context-bank";
|
||||
label = "venus_sec_bitstream";
|
||||
iommus = <&apps_smmu 0x2181 0x0404>;
|
||||
qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-pagetable = "LLC";
|
||||
qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
|
||||
virtual-addr-pool = <0x00500000 0xdfb00000>;
|
||||
qcom,secure-context-bank;
|
||||
};
|
||||
|
||||
secure_pixel_cb {
|
||||
compatible = "qcom,msm-vidc,context-bank";
|
||||
label = "venus_sec_pixel";
|
||||
iommus = <&apps_smmu 0x2183 0x0400>;
|
||||
qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-pagetable = "LLC";
|
||||
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
||||
virtual-addr-pool = <0x00500000 0xdfb00000>;
|
||||
qcom,secure-context-bank;
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user