mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-01-28 16:30:37 +00:00
ARM: dts: msm: Add initial device tree for Holi
Adding initial device tree support for holi target. Change-Id: Id5bc80a3ba916424650c993b2a52d080b1a1b2cb
This commit is contained in:
Yogesh Lal
@@ -80,6 +80,9 @@ SoCs:
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- SDMMAGPIE
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compatible = "qcom,sdmmagpie"
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- HOLI
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compatible = "qcom,holi"
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Generic board variants:
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- CDP device:
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@@ -216,3 +219,4 @@ compatible = "qcom,sdxprairie-cdp"
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compatible = "qcom,sdmmagpie-rumi"
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compatible = "qcom,sdmmagpie-idp"
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compatible = "qcom,sdmmagpie-qrd"
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compatible = "qcom,holi-rumi"
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@@ -34,6 +34,14 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \
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lahainap-qrd.dtb
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endif
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ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
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dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo
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holi-rumi-overlay.dtbo-base := holi.dtb
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else
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dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb
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endif
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ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
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dtbo-$(CONFIG_ARCH_SHIMA) += \
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shima-rumi-overlay.dtbo
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11
qcom/holi-rumi-overlay.dts
Normal file
11
qcom/holi-rumi-overlay.dts
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@@ -0,0 +1,11 @@
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/dts-v1/;
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/plugin/;
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#include "holi-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Holi RUMI";
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compatible = "qcom,holi-rumi", "qcom,holi", "qcom,rumi";
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qcom,msm-id = <454 0x10000>;
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qcom,board-id = <15 0>;
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};
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11
qcom/holi-rumi.dts
Normal file
11
qcom/holi-rumi.dts
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@@ -0,0 +1,11 @@
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/dts-v1/;
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/memreserve/ 0x50000000 0x00000100;
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#include "holi.dtsi"
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#include "holi-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Holi RUMI";
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compatible = "qcom,holi-rumi", "qcom,holi", "qcom,rumi";
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qcom,board-id = <15 0>;
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};
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13
qcom/holi-rumi.dtsi
Normal file
13
qcom/holi-rumi.dtsi
Normal file
@@ -0,0 +1,13 @@
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&soc {
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timer {
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clock-frequency = <500000>;
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};
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timer@f420000 {
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clock-frequency = <500000>;
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};
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wdog {
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status = "disabled";
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};
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};
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9
qcom/holi.dts
Normal file
9
qcom/holi.dts
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@@ -0,0 +1,9 @@
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/dts-v1/;
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#include "holi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Holi SoC";
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compatible = "qcom,holi";
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qcom,board-id = <0 0>;
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};
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369
qcom/holi.dtsi
Normal file
369
qcom/holi.dtsi
Normal file
@@ -0,0 +1,369 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. Holi";
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compatible = "qcom,holi";
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qcom,msm-id = <454 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x50000000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x100000>;
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x50000000>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x50000000>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x50000000>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x50000000>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x50000000>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x10000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cache-size = <0x10000>;
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cpu-release-addr = <0x0 0x50000000>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cache-size = <0x10000>;
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cpu-release-addr = <0x0 0x50000000>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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soc: soc { };
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chosen {
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bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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intc: interrupt-controller@f200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0xf200000 0x10000>, /* GICD */
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<0xf240000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@f420000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x0f420000 0x1000>;
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clock-frequency = <19200000>;
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frame@f421000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0f421000 0x1000>,
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<0x0f422000 0x1000>;
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};
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frame@f423000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf243000 0x1000>;
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status = "disabled";
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};
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frame@f425000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf425000 0x1000>;
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status = "disabled";
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};
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frame@f427000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf427000 0x1000>;
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status = "disabled";
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};
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frame@f429000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf429000 0x1000>;
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status = "disabled";
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};
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frame@f42b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf42b000 0x1000>;
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status = "disabled";
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};
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frame@f42d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf42d000 0x1000>;
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status = "disabled";
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};
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};
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cpu_pmu: cpu-pmu {
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compatible = "arm,armv8-pmuv3";
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qcom,irq-is-percpu;
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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qcom,msm-imem@c125000 {
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compatible = "qcom,msm-imem";
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reg = <0xc125000 0x1000>;
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ranges = <0x0 0xc125000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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dload_type@1c {
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compatible = "qcom,msm-imem-dload-type";
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reg = <0x1c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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kaslr_offset@6d0 {
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compatible = "qcom,msm-imem-kaslr_offset";
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reg = <0x6d0 0xc>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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diag_dload@c8 {
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compatible = "qcom,msm-imem-diag-dload";
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reg = <0xc8 0xc8>;
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};
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};
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restart@440b000 {
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compatible = "qcom,pshold";
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reg = <0x440b000 0x4>, <0x03d3000 0x4>;
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reg-names = "pshold-base", "tcsr-boot-misc-detect";
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};
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qcom,msm-rtb {
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compatible = "qcom,msm-rtb";
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qcom,rtb-size = <0x100000>;
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};
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wdog: qcom,wdt@f410000 {
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compatible = "qcom,msm-watchdog";
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reg = <0xf410000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 1 IRQ_TYPE_LEVEL_HIGH>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <9360>;
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qcom,ipi-ping;
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qcom,wakeup-enable;
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};
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ipcc_mproc: qcom,ipcc@208000 {
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compatible = "qcom,ipcc";
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reg = <0x208000 0x1000>;
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interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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};
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