Update the QMP phy init sequence as per the HSR v1.08 and HSR v0.94
update for DP Combo phy and Uni Phy respectively.
Change-Id: I0fd5bd28abe2db64106bf17ff6480ef13f77612e
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn used by EAS to take
placement decisions.
Change-Id: Ia44ffe4fcb799663c4bb47eb18f1ac79952ed12d
Add the DT property "regulator-allow-set-load" for PM8350B IBB
regulator device that is required to support some consumer APIs.
Change-Id: I0a54c4bb7b4e3b6234d36072041ee78fde4774d5
Add documentation for CPU voltage cooling device. CPU voltage cooling
device will provide support to apply CPU frequency mitigation on the
different CPUs in a cluster to achieve a reduction in cluster voltage.
This is achieved by building a mitigation table mapping the CPU
frequency levels to a voltage.
Change-Id: I41a222c54442bdc065267f1f1cf079118b8032e9
Tuning for Tx 3.1 Gen2 needs to be done by modifiying the deemph
registers. Expose these registers via device tree properties so that
tuning can be applied duing dwc3 init.
Change-Id: I84066e976ccbd6006ca9149e29d1c27acb694646
The register address range for Lahaina is not covering all the
controller registers. Tuning the Tx deemph registers for dwc3
gen2 protocol test is not possible with the current range.
Modify the reg property to cover the entire range as defined in
the data book to fix this issue.
Change-Id: I34b605f920af7cae8b2efd69a54f96e8cde5c001
Output of PWM channel 4 is used for external backlight control of
display panel. Add pinctrl configuration for PM8350C GPIO 9 such that
it is capable of outputting PWM 4's output. This pinctrl configuration
is used by display driver for external backlight control.
Change-Id: Ie9e1a1bf02d8caecde61861dc4528fa0f414a995
Add qcom,msm-hang-detect to device tree to enable MSM Core Hang
Detection on all cores.
Changed from 2 nodes (one for each of silver and gold) to
1 node because that's semantically correct for the driver.
Change-Id: I063d7cc244a0b5d12971f393f45053914fa53179
Use 'dma-coherent-hint-cached' instead of 'dma-coherent' for the
fastrpc iommu context banks.
Now, on a QGKI kernel, cached ION buffers will be DMA mapped as
IOMMU cached for the fastrpc devices, all other buffers will be
DMA mapped as IOMMU uncached and dma_alloc_attrs will always
return memory with a cached CPU mapping as well as DMA mapping
its memory as IOMMU cached.
On a GKI kernel, all buffers for fastrpc devices will be DMA
mapped as IOMMU uncached and dma_alloc_attrs will always return
CPU uncached memory.
Change-Id: I4c5b3e082dc057cb76bfd039b19c6211c729597f
Acked-by: Thyagarajan Venkatanarayanan <venkatan@qti.qualcomm.com>
