hyp core control driver provides machanism to reserve CPUs
as needed by other virtual machines in the system.
Change-Id: Id7bc3d7e0df3c400d9e2db810b3dad84589a8afa
This change configures sleep state of UART RX line into GPIO mode to
support the wakeup feature. Pinctrl driver and wakeup functionality
expects PIN to be in gpio mode.
Change-Id: If4133645023050bf93b96ba8c358baa1ef87f3e6
Add "qcom,protection-domain" to PMIC Glink device so that it can
handle protection domain restart (PDR) notifications and pass the
state transitions to its clients on Waipio platforms.
Change-Id: Id7288f4548abac1a774dd5ffdb695415d69f00d6
Add "qcom,subsys-name" to PMIC Glink device so that it can handle
SSR notifications and pass the state transitions to its clients
on Waipio platforms.
Change-Id: Ibd3f52d2c6689447723bb4e868b6080896cb58bb
Incorrect SID offset was causing an error when device
is sending data to the host on PCIe RC1 port.
Fix the base SID so the correct BDF to SID mapping
is generated on the PCIe RC1 port.
Change-Id: I0d0e4affc018c9d45acc8233506581f5cf4d0b88
The secure display region was kept around during the transition phase
from ION to dma-buf heaps. Now that the transition is complete, ION
has been removed, and the secure display region was absorbed into
the non-secure display region, we can remove the now unused region,
and stop including Lahaina's ION devicetree file.
Also, it has been observed that the kernel reorders the CMA regions
prior to allocating the memory for each region. This reordering can
cause smaller CMA regions to be allocated before bigger CMA regions,
resulting in failure to allocate the bigger CMA regions, as the memory
in the lower 4 GB becomes too fragmented. To mitigate this, assign a
region in memory to the non-secure CMA display region.
Change-Id: I27ca5b7115abd4620ae06ef588629f5fe19b020a
Add a Glink SPMI debug controller device which can be used to
read and write PMIC registers over PMIC Glink using a remote
subsytem (e.g. DSP). It provides access to PMICs on both the
primary and secondary SPMI bus.
Change-Id: I6a1a747bbafc83622590380e1a4b84834c6cc56f
Add handle to the EUD clkref, so that the EUD driver can vote for this
to be on/off depending on the EUD state.
Change-Id: Idfbaeacf58d7f4fc8c2cdd3f23e8ef6690507314
Add charger thermal mitigation levels for Waipio MTP and QRD so
that thermal SW can set CHARGE_CONTROL_LIMIT property in battery
power supply for thermal mitigation.
Change-Id: I339d2fb4ee9cac06e7120881e3a964fecd4edace
The allocation range for the default CMA region was limited to
0x0 -- 0xdfffffff on Lahaina since otherwise the physical address
of memory allocated for the modem from HLOS could overlap with the
CLADE address space on the modem. The CLADE address space has now
moved to reside within the 4 GB -- 5 GB range on Waipio, so there is
no need to limit the allocation ranges for the default CMA region.
Change-Id: I8efe6cec979d89b972fc8f248bb1e1e82f43243f
The gpu_cc_gx_gdsc itself requires VDD_GFX, but it'll handshake with a
clock as part of its enable/disable sequence which requires VDD_MXC.
VDD_MXC is necessary for the handshake to complete.
Change-Id: Iec2b7cd975ec5dc29ba5bf471c52fb1e7ee43612
