On neo due to slow eMMC part load percentage is going above 35% leading
to scale up and NOM corener and power team reported some power
concerns.
Enable this device tree property to set scale up threshold to 75 for
slower eMMC targets.
Change-Id: I43a7b258315bbc1e4e7182e30ba648c4a509cb4d
SDHCI timeout waiting for HW interrupt has been observed with the following
dll_usr_ctrl settings -> 0x090106C0
By updating dll_usr_ctrl to 0x2c010800 issue not seen.
Change-Id: I73fe6028b14813d2ba10275ec58bf42162f84104
Increased the left eye and right eye dma heap
pool size to 16MB to support higher resolution
based buffers in case of neo.
Change-Id: I8e9bc09ecc89073cde657c9dc9ff4d6bd3e34de5
In view of issues observed on Gen-1 targets where letting the PIPECTL
SUSPHY bit stay set during controller initialization causing the HW
to access 0th address after setting run_stop bit, add disable u3
susphy quirk to ensure this bit is not set during dwc3 probe.
Change-Id: I6e19b7dc64e3f683a1f66ff9b05ea9a09d5e5e9f
Add alias naming for cpu pause cooling device.
Add alias naming for cpu hotplug cooling device.
Add changes for cpufreq driver node.
Change-Id: I9cbb6beceff0a83976672df3783d49ab3add6e40
IPA handle for HP11 target via s1f rails and s1f rails source with
external GPIO 7, Hence updated vreg rails based on GPIO 7.
Change-Id: Idfd6cf3cc766bd7200cc7ae6eca34ca8f9fb4127
Current properties "qcom,threshold-arr" and "qcom,config-arr"
assumes that logical CPU number & physical CPU has 1:1
mapping and accordingly all the registers placed linearly with
increasing order of logical CPU numbers.
But if any CPU is not available then 1:1 mapping is broken
as we are having logically contiguous CPU numbers even if
physical cpus are not available.
To resolve this we are replacing old properties with a new property
"qcom,chd-percpu-info" and map core-hang registers wrt to CPU phandles.
The format is <&CPUx_Phandle CPUx_Threshold CPUx_Config>.
Change-Id: I17864c4e5b0a2739cf60e3dd2fdc264f778c083e
Binding properties "qcom,threshold-arr" and "qcom,config-arr"
assumes that logical CPU number & physical CPU has 1:1 mapping
which is not true when any CPU is not available.
To resolve this we are replacing old properties with a new property
"qcom,chd-percpu-info" and map core-hang registers wrt to CPU phandles.
The format is <&CPUx_Phandle CPUx_Threshold CPUx_Config>.
Change-Id: Ib5ce47b5969e1203e6508e6c77dfdc8b6d7de65d
Adding a change to clear __GFP_RETRY_MAY_FAIL flag for
order-3 tmp_alloc rather use __GFP_NORETRY flag to retry
only once whenever there is an order-2 fallback option
available. So, that it may help in replenishing
the buffers on time.
Change-Id: I44f16a121eb2769077bb6ac903b0c4895afa00f8
